From 66a72ff64c46d8a9fdade77223de62b4dcfe2825 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 21 Dec 2016 14:33:07 -0800
Subject: Add Analog type

Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)
---
 chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'chiselFrontend/src/main/scala/chisel3/internal')

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 50400034..bee72817 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -263,6 +263,7 @@ case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command
 case class WhenEnd(sourceInfo: SourceInfo) extends Command
 case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
 case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command
+case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command
 case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
 case class Stop(sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Command
 case class Port(id: Data, dir: Direction)
-- 
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