diff options
| author | Jim Lawson | 2016-09-23 16:50:39 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-09-23 16:50:39 -0700 |
| commit | 3e174cc55be350a06e6e95ac6505a77167bd5a29 (patch) | |
| tree | 01813d93be83432a7c13fed6b1f56d9b9b942ca0 /chiselFrontend/src/main/scala/chisel3/internal | |
| parent | 9c88d767e04ac25ab72380c39f30e39c83abf563 (diff) | |
| parent | 785620b1403d827986bf60c2a001d8d6f71eed72 (diff) | |
Merge branch 'master' into gsdt
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index 1f05b6e2..0641686c 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -42,6 +42,7 @@ object PrimOp { val ConvertOp = PrimOp("cvt") val AsUIntOp = PrimOp("asUInt") val AsSIntOp = PrimOp("asSInt") + val AsClockOp = PrimOp("asClock") } abstract class Arg { @@ -166,9 +167,9 @@ case class WhenEnd(sourceInfo: SourceInfo) extends Command case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command -case class Stop(sourceInfo: SourceInfo, clk: Arg, ret: Int) extends Command +case class Stop(sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Command case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg case class Port(id: Data, dir: Direction) -case class Printf(sourceInfo: SourceInfo, clk: Arg, pable: Printable) extends Command +case class Printf(sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Command case class Circuit(name: String, components: Seq[Component]) |