diff options
| author | Jim Lawson | 2016-08-17 13:30:05 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-08-17 13:41:43 -0700 |
| commit | 7922f8d4998dd902ee18a6e85e4a404a1f29eb3f (patch) | |
| tree | acabde9aa9c81dc3620dc501f89bcb674bdfe19b /chiselFrontend/src/main/scala/chisel3/internal | |
| parent | f41f2533c55e506f7d5bf2ee0198de4d9a3dbea3 (diff) | |
Rocket-chip updates.
Assume LHSItOutput if neither side is driving.
Restore Wire()'s removal of direction in binding.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala index b809b8fe..93879950 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala @@ -19,4 +19,5 @@ class CompileOptions(optionsMap: Map[String, String]) { val portDeterminesDirection: Boolean = optionsMap.getOrElse("portDeterminesDirection", looseDefault).toBoolean val internalConnectionToInputOk: Boolean = optionsMap.getOrElse("internalConnectionToInputOk", looseDefault).toBoolean val tryConnectionsSwapped: Boolean = optionsMap.getOrElse("tryConnectionsSwapped", looseDefault).toBoolean + val assumeLHSIsOutput: Boolean = optionsMap.getOrElse("assumeLHSIsOutput", looseDefault).toBoolean } |