Rocket-chip updates.

Assume LHSItOutput if neither side is driving.
Restore Wire()'s removal of direction in binding.

4 files changed, 11 insertions, 5 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index b7fd65a5..c40b85ad 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -188,7 +188,13 @@ object BiConnect {
             throw BothDriversException
           }
         }
-        case (None,         None)         => throw UnknownDriverException
+        case (None,         None)         => {
+          if (compileOptions.assumeLHSIsOutput) {
+            issueConnectR2L(left, right)
+          } else {
+            throw UnknownDriverException
+          }
+        }
       }
     }
 
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binder.scala b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala
index 08c0519e..c7346dce 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Binder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binder.scala
@@ -58,8 +58,7 @@ case class RegBinder(enclosure: Module) extends Binder[RegBinding] {
   def apply(in: UnboundBinding) = RegBinding(enclosure)
 }
 
-// Notice how WireBinder uses the direction of the UnboundNode
 case class WireBinder(enclosure: Module) extends Binder[WireBinding] {
-  def apply(in: UnboundBinding) = WireBinding(enclosure, in.direction)
+  def apply(in: UnboundBinding) = WireBinding(enclosure)
 }
 
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
index 555ba4d5..da678fed 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
@@ -207,5 +207,5 @@ case class PortBinding(enclosure: Module, direction: Option[Direction])
 case class RegBinding(enclosure: Module)
     extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding
 
-case class WireBinding(enclosure: Module, direction: Option[Direction])
-    extends SynthesizableBinding with ConstrainedBinding
+case class WireBinding(enclosure: Module)
+    extends SynthesizableBinding with ConstrainedBinding with UndirectionedBinding
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
index b809b8fe..93879950 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
@@ -19,4 +19,5 @@ class CompileOptions(optionsMap: Map[String, String]) {
   val portDeterminesDirection: Boolean = optionsMap.getOrElse("portDeterminesDirection", looseDefault).toBoolean
   val internalConnectionToInputOk: Boolean = optionsMap.getOrElse("internalConnectionToInputOk", looseDefault).toBoolean
   val tryConnectionsSwapped: Boolean = optionsMap.getOrElse("tryConnectionsSwapped", looseDefault).toBoolean
+  val assumeLHSIsOutput: Boolean = optionsMap.getOrElse("assumeLHSIsOutput", looseDefault).toBoolean
 }