summaryrefslogtreecommitdiff
path: root/chiselFrontend/src/main/scala/chisel3/internal
diff options
context:
space:
mode:
authorChick Markley2016-10-25 08:59:15 -0700
committerGitHub2016-10-25 08:59:15 -0700
commite00ae6ff3518d517733f5cfe3959e8b31c5876b5 (patch)
tree93063422d03f13c6585b7a582dcf24c1f27b0b6a /chiselFrontend/src/main/scala/chisel3/internal
parenta44c7aede6902533ea79fcf6a3fbed234b4456c0 (diff)
FixedPoint number support for chisel3 (#328)
* FixedPoint number support for chisel3 FixedPoint numbers have a width and a binary position Either, neither or both maybe inferred. Firrtl will convert these to SInts during lowering passes * Fixes based on Jack's comments on PR #328 * Add experimental warning to FixedPoint class and object * Fixed comment per Adam's comment on PR #328
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala47
1 files changed, 47 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 0641686c..0f866c27 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -42,6 +42,8 @@ object PrimOp {
val ConvertOp = PrimOp("cvt")
val AsUIntOp = PrimOp("asUInt")
val AsSIntOp = PrimOp("asSInt")
+ val AsFixedPointOp = PrimOp("asFixedPoint")
+ val SetBinaryPoint = PrimOp("bpset")
val AsClockOp = PrimOp("asClock")
}
@@ -85,6 +87,14 @@ case class SLit(n: BigInt, w: Width) extends LitArg(n, w) {
def minWidth: Int = 1 + n.bitLength
}
+case class FPLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) {
+ def name: String = {
+ val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n
+ s"asFixedPoint(${ULit(unsigned, width).name}, ${binaryPoint.asInstanceOf[KnownBinaryPoint].value})"
+ }
+ def minWidth: Int = 1 + n.bitLength
+}
+
case class Ref(name: String) extends Arg
case class ModuleIO(mod: Module, name: String) extends Arg {
override def fullName(ctx: Component): String =
@@ -136,6 +146,43 @@ sealed case class KnownWidth(value: Int) extends Width {
override def toString: String = s"<${value.toString}>"
}
+object BinaryPoint {
+ def apply(x: Int): BinaryPoint = KnownBinaryPoint(x)
+ def apply(): BinaryPoint = UnknownBinaryPoint
+}
+
+sealed abstract class BinaryPoint {
+ type W = Int
+ def max(that: BinaryPoint): BinaryPoint = this.op(that, _ max _)
+ def + (that: BinaryPoint): BinaryPoint = this.op(that, _ + _)
+ def + (that: Int): BinaryPoint = this.op(this, (a, b) => a + that)
+ def shiftRight(that: Int): BinaryPoint = this.op(this, (a, b) => 0 max (a - that))
+ def dynamicShiftLeft(that: BinaryPoint): BinaryPoint =
+ this.op(that, (a, b) => a + (1 << b) - 1)
+
+ def known: Boolean
+ def get: W
+ protected def op(that: BinaryPoint, f: (W, W) => W): BinaryPoint
+}
+
+case object UnknownBinaryPoint extends BinaryPoint {
+ def known: Boolean = false
+ def get: Int = None.get
+ def op(that: BinaryPoint, f: (W, W) => W): BinaryPoint = this
+ override def toString: String = ""
+}
+
+sealed case class KnownBinaryPoint(value: Int) extends BinaryPoint {
+ def known: Boolean = true
+ def get: Int = value
+ def op(that: BinaryPoint, f: (W, W) => W): BinaryPoint = that match {
+ case KnownBinaryPoint(x) => KnownBinaryPoint(f(value, x))
+ case _ => that
+ }
+ override def toString: String = s"<<${value.toString}>>"
+}
+
+
sealed abstract class MemPortDirection(name: String) {
override def toString: String = name
}