| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-08-24 | Removed old chisel3 tests that all failed for syntax reasons. Tests should ↵ | azidar | |
| now be small examples, categorized by either passes, errors, or features. | |||
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. ↵ | azidar | |
| Added Long support so UInt(LARGENUMBER) works | |||
| 2015-05-21 | Added pad pass, used for flo backend | azidar | |
| 2015-05-01 | Fixed bug where the enable was looked at for lowering MUX. | azidar | |
| 2015-04-29 | Fixed bug in lowering of subfields. Fixed ModuleVec.fir to be correct | azidar | |
| 2015-04-28 | Instances are now male. Reworked lowering pass to be sane. ↵ | azidar | |
| chisel3/ModuleVec.fir doesn't work because incorrecly generated? | |||
| 2015-04-22 | Added new test that breaks current parser. updated todo | azidar | |
| 2015-04-20 | Fixed tests to use new execution arguments. Added and fixed chisel3 bugs | azidar | |
| 2015-04-16 | Updated parser to correctly read empty statements | azidar | |
| 2015-04-13 | new chisel3 tests | jackbackrack | |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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