diff options
| author | azidar | 2015-05-01 11:02:46 -0700 |
|---|---|---|
| committer | azidar | 2015-05-01 11:02:46 -0700 |
| commit | 0a00a6aaa846b695a7a750cf40079d56a9bb94d6 (patch) | |
| tree | b9d940fefdfdcd04afb6e88906bff6ee6c229244 /test/chisel3/ModuleVec.fir | |
| parent | a0834153e1e5a506dc66d8d792f6f9594052b546 (diff) | |
Fixed bug where the enable was looked at for lowering MUX.
Diffstat (limited to 'test/chisel3/ModuleVec.fir')
| -rw-r--r-- | test/chisel3/ModuleVec.fir | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir index a4617267..a53c9549 100644 --- a/test/chisel3/ModuleVec.fir +++ b/test/chisel3/ModuleVec.fir @@ -21,9 +21,9 @@ circuit ModuleVec : inst T_37 of PlusOne inst T_38 of PlusOne_25 - wire pluses : { in : UInt<32>, flip out : UInt<32>}[2] - pluses[0] := Pad(T_37,?) - pluses[1] := Pad(T_38,?) + wire pluses : { flip in : UInt<32>, out : UInt<32>}[2] + pluses[0] := T_37 + pluses[1] := T_38 pluses[0].in := Pad(ins[0],?) outs[0] := Pad(pluses[0].out,?) pluses[1].in := Pad(ins[1],?) |