Fixed bug where the enable was looked at for lowering MUX.

5 files changed, 73 insertions, 13 deletions

diff --git a/TODO b/TODO
index f7863055..d651b479 100644
--- a/TODO
+++ b/TODO
@@ -6,6 +6,9 @@
 Update spec
 <>
 Add Unit Tests for each pass
+   Separate passes into discrete chunks
+   Push all tests entirely through
+   Check after each pass
    
 ======== Update Core ==========
 Add source locaters
@@ -53,6 +56,7 @@ Stephen:
       pin stephen on an example
 Patrick: 
    move Infer-Widths to before vec expansion?
+   talk about primops
 
 ======== Think About ========
 <>
@@ -111,10 +115,14 @@ Schedulable
 Scheduler
 
 ======== Notes ========
-Only for MUXES can width inference go backwards:
+Only for MUXES, AS, and __ can width inference go backwards:
   reg r : UInt<5>
   r := MUX(p,UInt<?>(1),UInt<?>(2))
   ==>
   reg r : UInt<5>
   r := MUX(p,UInt<5>(1),UInt<5>(2))
 
+
+Which ones
+Treat everything as just bits - the only operators that should exist are ones that emit different bits
+Go through all primops with Andrew
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 4c706087..e67ec21f 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -729,12 +729,6 @@ defn expand-expr (e:Expression) -> List<EF> :
             val len = num-elems(type(e))
             val ret = headn(tailn(exps,begin),len)
             for r in ret map : EF(exp(r),DEFAULT)
-            ;val b =  exp(e)
-            ;val exps = for x in generate-entry(name(b as WRef),type(b)) map :
-               ;EF(WRef(name(x),type(x),NodeKind(),gender(e)),DEFAULT)
-            ;val begin = index-of-elem(type(b) as BundleType,name(e))
-            ;val len = num-elems(type(e))
-            ;headn(tailn(exps,begin),len)
       (e:WIndex) :
          val exps = expand-expr(exp(e))
          val len = num-elems(type(e))
@@ -755,8 +749,6 @@ defn lower-ports (ports:List<Port>) -> List<Port> :
 defn type (s:WDefAccessor) -> Type : type(type(source(s)) as VectorType)
 defn size (s:DefMemory) -> Int : size(type(s))
 defn size (s:WDefAccessor) -> Int : size(type(source(s)) as VectorType)
-defn kind (e:WSubfield) -> Kind : kind(exp(e) as WRef|WSubfield|WIndex)
-defn kind (e:WIndex) -> Kind : kind(exp(e) as WRef|WSubfield|WIndex)
 defn base-name (e:Expression) -> Symbol :
    match(e) : 
       (e:WRef) : name(e)
diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza
index 60868799..b293da52 100644
--- a/src/main/stanza/primop.stanza
+++ b/src/main/stanza/primop.stanza
@@ -182,7 +182,7 @@ public defn lower-and-type-primop (e:DoPrim) -> DoPrim :
       NEQUAL-SS-OP      : DoPrim(op(e),args(e),consts(e),u())
       MUX-OP           : 
          DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
-            match(type(args(e)[0]),type(args(e)[1])) :
+            match(type(args(e)[1]),type(args(e)[2])) :
                (t1:UIntType, t2:UIntType) : MUX-UU-OP
                (t1:SIntType, t2:SIntType) : MUX-SS-OP
       MUX-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
index a4617267..a53c9549 100644
--- a/test/chisel3/ModuleVec.fir
+++ b/test/chisel3/ModuleVec.fir
@@ -21,9 +21,9 @@ circuit ModuleVec :
     
     inst T_37 of PlusOne
     inst T_38 of PlusOne_25
-    wire pluses : { in : UInt<32>, flip out : UInt<32>}[2]
-    pluses[0] := Pad(T_37,?)
-    pluses[1] := Pad(T_38,?)
+    wire pluses : { flip in : UInt<32>, out : UInt<32>}[2]
+    pluses[0] := T_37
+    pluses[1] := T_38
     pluses[0].in := Pad(ins[0],?)
     outs[0] := Pad(pluses[0].out,?)
     pluses[1].in := Pad(ins[1],?)
diff --git a/test/chisel3/SIntOps.fir b/test/chisel3/SIntOps.fir
new file mode 100644
index 00000000..f79d0fca
--- /dev/null
+++ b/test/chisel3/SIntOps.fir
@@ -0,0 +1,60 @@
+; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
+
+circuit SIntOps : 
+  module SIntOps : 
+    input a : SInt<16>
+    input b : SInt<16>
+    output addout : SInt<16>
+    output subout : SInt<16>
+    output timesout : SInt<16>
+    output divout : SInt<16>
+    output modout : SInt<16>
+    output lshiftout : SInt<16>
+    output rshiftout : SInt<16>
+    output lessout : UInt<1>
+    output greatout : UInt<1>
+    output eqout : UInt<1>
+    output noteqout : UInt<1>
+    output lesseqout : UInt<1>
+    output greateqout : UInt<1>
+    output negout : SInt<16>
+    
+    wire ub : UInt
+    ub := b
+    node T_44 = add-wrap(Pad(a,?), Pad(b,?))
+    addout := Pad(T_44,?)
+    node T_45 = sub-wrap(Pad(a,?), Pad(b,?))
+    subout := Pad(T_45,?)
+    node T_46 = mul(Pad(a,?), Pad(b,?))
+    node T_47 = bits(T_46, 15, 0)
+    timesout := Pad(T_47,?)
+    node T_48 = eq(Pad(b,?), Pad(SInt<1>(0),?))
+    node T_49 = mux(Pad(T_48,?), Pad(SInt<2>(1),?), Pad(b,?))
+    node T_50 = div(Pad(a,?), Pad(T_49,?))
+    divout := Pad(T_50,?)
+    modout := Pad(UInt<1>(0),?)
+    node T_51 = bits(ub, 3, 0)
+    node T_52 = dshl(a, T_51)
+    node T_53 = bits(T_52, 15, 0)
+    wire T_54 : SInt
+    T_54 := T_53
+    lshiftout := Pad(T_54,?)
+    node T_55 = dshr(a, ub)
+    wire T_56 : SInt
+    T_56 := T_55
+    rshiftout := Pad(T_56,?)
+    node T_57 = lt(Pad(a,?), Pad(b,?))
+    lessout := Pad(T_57,?)
+    node T_58 = gt(Pad(a,?), Pad(b,?))
+    greatout := Pad(T_58,?)
+    node T_59 = eq(Pad(a,?), Pad(b,?))
+    eqout := Pad(T_59,?)
+    node T_60 = neq(Pad(a,?), Pad(b,?))
+    noteqout := Pad(T_60,?)
+    node T_61 = leq(Pad(a,?), Pad(b,?))
+    lesseqout := Pad(T_61,?)
+    node T_62 = geq(Pad(a,?), Pad(b,?))
+    greateqout := Pad(T_62,?)
+    node T_63 = sub-wrap(Pad(SInt<1>(0),?), Pad(a,?))
+    negout := Pad(T_63,?)