Fixed assignment to outputs not getting emitted from Expand When pass

2 files changed, 29 insertions, 1 deletions

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 5d1848f0..4c706087 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1088,7 +1088,17 @@ defn reduce-or (l:List<Expression>) -> Expression :
 ; kinds:  Used to know the kind of reference, so we know whether we should error if it isn't initialized. We also know how we should declare the refernce.
 ; enables:Calculated off of assigns.
 
-; I think I'm going to restructure this so that not all information is held in the tables, but instead, we walk the graph again, and do stuff on declarations, and delete other stuff
+
+defn expand-whens (ports:List<Port>, table:HashTable<Symbol,SymbolicValue>,cons:Vector<Stmt>) -> False :
+   for p in ports do :
+      if direction(p) == OUTPUT :
+         val ref = WRef(name(p),type(p),PortKind(),FEMALE)
+         add{cons,_} $ 
+            if has-nul?(table[name(p)]) : 
+               println("Uninitialized: ~" % [to-string(name(p))]);TODO actually collect error
+               EmptyStmt()
+            else : Connect(ref,to-exp(table[name(p)]) as Expression)
+
 defn expand-whens (s:Stmt, table:HashTable<Symbol,SymbolicValue>,decs:Vector<Stmt>,cons:Vector<Stmt>) -> Stmt :
    match(map(expand-whens{_,table,decs,cons},s)) : 
       (s:DefNode|DefMemory) : add(decs,s)
@@ -1277,6 +1287,7 @@ defn expand-whens (m:Module) -> Module :
    for x in table do : println-debug(x)
    val decs = Vector<Stmt>()
    val cons = Vector<Stmt>()
+   expand-whens(ports(m),table,cons)
    expand-whens(body(m),table,decs,cons)
    Module(name(m),ports(m),Begin(append(to-list(decs),to-list(cons))))
 
diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir
new file mode 100644
index 00000000..839a8590
--- /dev/null
+++ b/test/passes/jacktest/Counter.fir
@@ -0,0 +1,17 @@
+; RUN: firrtl -i %s -o %s.flo -x X -p cTwd | tee %s.out | FileCheck %s
+; CHECK: Done!
+
+circuit Counter : 
+  module Counter : 
+    input inc : UInt<1>
+    output tot : UInt<8>
+    input amt : UInt<4>
+    
+    reg T_13 : UInt<8>
+    on-reset T_13 := Pad(UInt<8>(0),?)
+    when inc : 
+      node T_14 = add-wrap(Pad(T_13,?), Pad(amt,?))
+      node T_15 = gt(Pad(T_14,?), Pad(UInt<8>(255),?))
+      node T_16 = mux(Pad(T_15,?), Pad(UInt<1>(0),?), Pad(T_14,?))
+      T_13 := Pad(T_16,?)
+    tot := Pad(T_13,?)