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authorazidar2015-04-20 12:08:10 -0700
committerazidar2015-04-20 12:08:10 -0700
commit7617e33993abf9f6be357e0261755a4736c2e085 (patch)
treea8a32a3e0d731b49173f1c6f02056aea20902ada /test/chisel3/ModuleVec.fir
parent130c6676418e85d5d4dd12a0f0845e912eda8c3e (diff)
Fixed tests to use new execution arguments. Added and fixed chisel3 bugs
Diffstat (limited to 'test/chisel3/ModuleVec.fir')
-rw-r--r--test/chisel3/ModuleVec.fir25
1 files changed, 0 insertions, 25 deletions
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
deleted file mode 100644
index e4c526ec..00000000
--- a/test/chisel3/ModuleVec.fir
+++ /dev/null
@@ -1,25 +0,0 @@
-circuit ModuleVec :
- module PlusOne :
- input in : UInt(32)
- output out : UInt(32)
-
- node T_34 : UInt(1) = UInt(1, 1)
- node T_35 : UInt(32) = add(in, T_34)
- out := T_35
- module PlusOne_26 :
- input in : UInt(32)
- output out : UInt(32)
-
- node T_36 : UInt(1) = UInt(1, 1)
- node T_37 : UInt(32) = add(in, T_36)
- out := T_37
- module ModuleVec :
- input ins : UInt(32)[2]
- output outs : UInt(32)[2]
-
- instance T_38 of PlusOne
- instance T_39 of PlusOne_26
- pluses.0.in := ins.0
- outs.0 := pluses.0.out
- pluses.1.in := ins.1
- outs.1 := pluses.1.out