diff options
| author | azidar | 2015-04-20 12:08:10 -0700 |
|---|---|---|
| committer | azidar | 2015-04-20 12:08:10 -0700 |
| commit | 7617e33993abf9f6be357e0261755a4736c2e085 (patch) | |
| tree | a8a32a3e0d731b49173f1c6f02056aea20902ada | |
| parent | 130c6676418e85d5d4dd12a0f0845e912eda8c3e (diff) | |
Fixed tests to use new execution arguments. Added and fixed chisel3 bugs
61 files changed, 250 insertions, 705 deletions
@@ -7,6 +7,9 @@ */*.swp */*/*.swp */*/*/*.swp +*/*/*.flo +*/*/*.out +*/*/*/*.flo src/lib/stanzam src/lib/stanza src/*/__MACOSX diff --git a/notes/frontend-notes.04.16.15.txt b/notes/frontend-notes.04.16.15.txt index 14634e5e..23da75d9 100644 --- a/notes/frontend-notes.04.16.15.txt +++ b/notes/frontend-notes.04.16.15.txt @@ -1,4 +1,18 @@ ======= Fixes to Jonathan's Front-end ====== + +== TODO == +Fixing chisel3 front-end bugs: + LFSR16: "concat" -> "cat" + MemorySearch: name collision with node done and output done + Mul: shr/shl take one expression argument, and one int argument. + node T_59 = UInt(2, 2) + node T_60 = shl(x, T_59) + ==> + node T_60 = shl(x, 2) + Outer: "instance" => "inst" + Stack: bug in firrtl! thanks! + +== Completed == Remove type from node emission Currently, these are not equivalent because we will fail a type check: @@ -10,4 +24,3 @@ Switch "input" -> "flip" and "output" to "" within a bundle Switch "add-mod" -> "add-wrap" Switch "multiplex" -> "mux" Switch "greater" -> "gt" - diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza index 991f7cf6..54fcb7f9 100644 --- a/src/main/stanza/firrtl-test-main.stanza +++ b/src/main/stanza/firrtl-test-main.stanza @@ -26,16 +26,24 @@ defn set-printvars! (p:List<Char>) : if contains(p,'g') : PRINT-GENDERS = true if contains(p,'c') : PRINT-CIRCUITS = true +;firrtl -i gcd.fir -o gcd.flo -x qabcefghipjklmno -p c defn main () : val args = commandline-arguments() - val lexed = lex-file(args[1]) + var input = false + var output = false + var passes = "qabcefghipjklmno" + var printvars = "" + for (s in args, i in 0 to false) do : + if s == "-i" : input = args[i + 1] + if s == "-o" : output = args[i + 1] + if s == "-x" : passes = args[i + 1] + if s == "-p" : printvars = args[i + 1] + if input == false : error("No input file provided. Use -i flag") + if output == false : error("No output file provided. Use -o flag") + val lexed = lex-file(input as String) val c = parse-firrtl(lexed) - if length(args) >= 4 : - set-printvars!(to-list(args[3])) - if length(args) >= 3 : - run-passes(c,to-list(args[2])) - else : - run-passes(c,to-list("qabcefghipjklmno")) + set-printvars!(to-list(printvars)) + run-passes(c,to-list(passes),output as String) main() diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index 789b94a3..2df09b8e 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -243,8 +243,8 @@ defmethod map (f: Expression -> Expression, e:Expression) -> Expression : (e:Subfield) : Subfield(f(exp(e)), name(e), type(e)) (e:Index) : Index(f(exp(e)), value(e), type(e)) (e:DoPrim) : DoPrim(op(e), map(f, args(e)), consts(e), type(e)) - (e:ReadPort) : ReadPort(f(mem(e)), f(index(e)), type(e), enable(e)) - (e:WritePort) : WritePort(f(mem(e)), f(index(e)), type(e), enable(e)) + (e:ReadPort) : ReadPort(f(mem(e)), f(index(e)), type(e), f(enable(e))) + (e:WritePort) : WritePort(f(mem(e)), f(index(e)), type(e), f(enable(e))) (e:Register) : Register(type(e),f(value(e)),f(enable(e))) (e) : e diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 24867612..f05f9482 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -716,8 +716,11 @@ defn lower (body:Stmt, table:HashTable<Symbol,List<KeyValue<Expression,Flip>>>) lower-stmt(s*) (s:Connect) : Begin{_} $ for (l in expand-expr(loc(s)), r in expand-expr(exp(s))) map : + println(s) val lgender = calc-gender(FEMALE,loc(s)) * value(l) val rgender = calc-gender(MALE,exp(s)) * value(r) + println(loc(s)) + println(exp(s)) switch fn ([x,y]) : lgender == x and rgender == y : [FEMALE,MALE] : Connect(key(l),key(r)) [MALE,FEMALE] : Connect(key(r),key(l)) @@ -1624,20 +1627,6 @@ defn replace-var-widths (c:Circuit,h:HashTable<Symbol,Int>) -> Circuit : Circuit(modules*,main(c)) -;defn remove-unknown-widths (c:Circuit) -> Circuit : -; defn remove-unknown-widths-w (w:Width) -> Width : -; match(w) : -; (w:UnknownWidth) : VarWidth(gensym(`w)) -; (w) : w -; val modules* = for m in modules(c) map : -; Module{name(m),_,body(m)} $ -; for p in ports(m) map : -; Port(name(p),direction(p),mapr(remove-unknown-widths-w,type(p))) -; -; val modules** = for m in modules* map : -; Module(name(m),ports(m),mapr(remove-unknown-widths-w,body(m))) -; Circuit(modules**,main(c)) - defn remove-unknowns-w (w:Width) -> Width : match(w) : (w:UnknownWidth) : VarWidth(gensym(`w)) @@ -1863,7 +1852,7 @@ defn flo-op-name (op:PrimOp) -> String : defn sane-width (wd:Width) -> Int : match(wd) : (w:IntWidth) : max(1, width(w)) - (w) : error("Unknown width") + (w) : error(string-join(["Unknown width: " w])) defn prim-width (type:Type) -> Int : match(type) : @@ -1875,96 +1864,98 @@ defn sizeof (in: Int) -> Int : ;; if in == 1: 1 else: to-int(ceil(log(in)/log(2))) max(1, ceil-log2(in)) -defn emit-all (o:OutputStream, es:Streamable, top:Symbol) : +defn emit-all (es:Streamable, top:Symbol) : for e in es do : match(e) : - (ex:Expression) : emit!(o,e,top) - (ex:String) : print(o, ex) - (ex:Symbol) : print(o, ex) - ;; (ex:Int) : print-all(o, [ex "'" sizeof(ex)]) - (ex:Int) : print(o, ex) - (ex) : print(o, ex) - -defn emit! (o:OutputStream, e:Expression,top:Symbol) : + (ex:Expression) : emit!(ex,top) + (ex:String) : print(ex) + (ex:Symbol) : print(ex) + ;; (ex:Int) : print-all([ex "'" sizeof(ex)]) + (ex:Int) : print(ex) + (ex) : print(ex) + +defn emit! (e:Expression,top:Symbol) : defn cmp-op? (op: PrimOp) -> True|False : contains?([EQUAL-OP, NEQUAL-OP, GREATER-OP, LESS-EQ-OP, LESS-OP, GREATER-EQ-OP], op) match(e) : - (e:Ref) : emit-all(o,[top "::" name(e)], top) - (e:UIntValue) : emit-all(o,[value(e) "'" sane-width(width(e))], top) - (e:SIntValue) : emit-all(o,[value(e) "'" sane-width(width(e))], top) - (e:Subfield) : emit-all(o,[exp(e) "/" name(e)], top) - (e:Index) : emit-all(o,[exp(e) "/" value(e)], top) + (e:Ref) : emit-all([top "::" name(e)], top) + (e:UIntValue) : emit-all([value(e) "'" sane-width(width(e))], top) + (e:SIntValue) : emit-all([value(e) "'" sane-width(width(e))], top) + (e:Subfield) : emit-all([exp(e) "/" name(e)], top) + (e:Index) : emit-all([exp(e) "/" value(e)], top) (e:Register) : - emit-all(o,["reg'" prim-width(type(e)) " " enable(e) " " value(e)], top) + emit-all(["reg'" prim-width(type(e)) " " enable(e) " " value(e)], top) (e:ReadPort) : - emit-all(o,["rd'" prim-width(type(e)) " " enable(e) " " mem(e) " " index(e)], top) + emit-all(["rd'" prim-width(type(e)) " " enable(e) " " mem(e) " " index(e)], top) (e:DoPrim) : if cmp-op?(op(e)) : - emit-all(o, [flo-op-name(op(e)) "'" prim-width(type(args(e)[0]))], top) + emit-all([flo-op-name(op(e)) "'" prim-width(type(args(e)[0]))], top) if op(e) == GREATER-OP or op(e) == LESS-EQ-OP : - emit-all(o, [" " args(e)[1] " " args(e)[0]], top) + emit-all([" " args(e)[1] " " args(e)[0]], top) else : - emit-all(o, [" " args(e)[0] " " args(e)[1]], top) + emit-all([" " args(e)[0] " " args(e)[1]], top) else if op(e) == BIT-SELECT-OP : - emit-all(o, [flo-op-name(op(e)) "'1 " args(e)[0] " " consts(e)[0]], top) + emit-all([flo-op-name(op(e)) "'1 " args(e)[0] " " consts(e)[0]], top) else if op(e) == BITS-SELECT-OP : val w = consts(e)[0] - consts(e)[1] + 1 - emit-all(o, [flo-op-name(op(e)) "'" w " " args(e)[0] " " consts(e)[1]], top) + emit-all([flo-op-name(op(e)) "'" w " " args(e)[0] " " consts(e)[1]], top) ;; else if op(e) == CONCAT-OP : ;; val w = consts(e)[0] - consts(e)[1] + 1 - ;; emit-all(o, [flo-op-name(op(e)) "'" w " " args(e)[0] " " consts(e)[1]], top) + ;; emit-all([flo-op-name(op(e)) "'" w " " args(e)[0] " " consts(e)[1]], top) else : - emit-all(o, [flo-op-name(op(e)) "'" prim-width(type(e))], top) + emit-all([flo-op-name(op(e)) "'" prim-width(type(e))], top) if op(e) == PAD-OP : - emit-all(o, [" " args(e)[0] " 0"], top) + emit-all([" " args(e)[0] " 0"], top) else : for arg in args(e) do : - print(o, " ") - emit!(o, arg, top) + print(" ") + emit!(arg, top) for const in consts(e) do : - print(o, " ") - print(o, const) - (e) : print-all(o, ["EMIT(" e ")"]) - ;(e) : emit-all(o, ["mov'" prim-width(type(e)) " " e], top) ;TODO, not sure which one is right + print(" ") + print(const) + (e) : print-all(["EMIT(" e ")"]) + ;(e) : emit-all(["mov'" prim-width(type(e)) " " e], top) ;TODO, not sure which one is right -defn emit-s (o:OutputStream, s:Stmt, v:List<Symbol>, top:Symbol) : +defn emit-s (s:Stmt, v:List<Symbol>, top:Symbol) : match(s) : (s:DefWire) : "" (s:DefInstance) : error("Shouldn't be here") (s:DefMemory) : val vtype = type(s) as VectorType - emit-all(o, [top "::" name(s) " = mem'" prim-width(type(vtype)) " " size(vtype) "\n"], top) - (s:DefNode) : emit-all(o, [top "::" name(s) " = " value(s) "\n"], top) - (s:Begin) : do(emit-s{o, _, v, top}, body(s)) + emit-all([top "::" name(s) " = mem'" prim-width(type(vtype)) " " size(vtype) "\n"], top) + (s:DefNode) : emit-all([top "::" name(s) " = " value(s) "\n"], top) + (s:Begin) : do(emit-s{_, v, top}, body(s)) (s:Connect) : if loc(s) typeof WritePort : val e = loc(s) as WritePort val name = gensym(`F) - emit-all(o, [top "::" name " = wr'" prim-width(type(e)) " " enable(e) " " top "::" mem(e) " " index(e) " " exp(s) "\n"], top) + emit-all([top "::" name " = wr'" prim-width(type(e)) " " enable(e) " " top "::" mem(e) " " index(e) " " exp(s) "\n"], top) else : val n = name(loc(s) as Ref) if contains?(v,n) : - emit-all(o, [n " = out'" prim-width(type(loc(s))) " " exp(s) "\n"], top) + emit-all([n " = out'" prim-width(type(loc(s))) " " exp(s) "\n"], top) else : - emit-all(o, [top "::" n " = " exp(s) "\n"], top) + emit-all([top "::" n " = " exp(s) "\n"], top) (s) : s -defn emit-module (o:OutputStream, m:Module) : +defn emit-module (m:Module) : val v = Vector<Symbol>() for port in ports(m) do : if name(port) ==`reset : - emit-all(o, [name(m) "::" name(port) " = rst'1\n"], name(m)) + emit-all([name(m) "::" name(port) " = rst'1\n"], name(m)) else : switch {_ == direction(port)} : - INPUT : print-all(o, [name(m) "::" name(port) " = " "in'" prim-width(type(port)) "\n"]) + INPUT : print-all([name(m) "::" name(port) " = " "in'" prim-width(type(port)) "\n"]) OUTPUT : add(v,name(port)) - emit-s(o, body(m), to-list(v), name(m)) + emit-s(body(m), to-list(v), name(m)) -public defn emit-flo (o:OutputStream, c:Circuit) : - emit-module(o, modules(c)[0]) +public defn emit-flo (file:String, c:Circuit) : + with-output-file{file, _} $ fn () : + emit-module(modules(c)[0]) + false c ;============= DRIVER ====================================== -public defn run-passes (c: Circuit, p: List<Char>) : +public defn run-passes (c: Circuit, p: List<Char>,file:String) : var c*:Circuit = c println("Compiling!") if PRINT-CIRCUITS : println("Original Circuit") @@ -1977,22 +1968,23 @@ public defn run-passes (c: Circuit, p: List<Char>) : ; Early passes: ; If modules have a reset defined, must be an INPUT and UInt(1) - if contains(p,'q') : do-stage("Temp Elimination", temp-elimination) - if contains(p,'a') : do-stage("Working IR", to-working-ir) - if contains(p,'b') : do-stage("Resolve Kinds", resolve-kinds) - if contains(p,'c') : do-stage("Make Explicit Reset", make-explicit-reset) - if contains(p,'e') : do-stage("Infer Types", infer-types) - if contains(p,'f') : do-stage("Resolve Genders", resolve-genders) - if contains(p,'g') : do-stage("Expand Accessors", expand-accessors) - if contains(p,'h') : do-stage("Lower To Ground", lower-to-ground) - if contains(p,'i') : do-stage("Expand Indexed Connects", expand-connect-indexed) - if contains(p,'p') : do-stage("Initialize Registers", initialize-registers) - if contains(p,'j') : do-stage("Expand Whens", expand-whens) - if contains(p,'k') : do-stage("Infer Widths", infer-widths) - if contains(p,'l') : do-stage("Inline Instances", inline-instances) - if contains(p,'m') : do-stage("Split Expressions", split-exp) - if contains(p,'n') : do-stage("Real IR", to-real-ir) - if contains(p,'o') : do-stage("To Flo", emit-flo{STANDARD-OUTPUT,_}) + if contains(p,'X') or contains(p,'a') : do-stage("Temp Elimination", temp-elimination) + if contains(p,'X') or contains(p,'b') : do-stage("Working IR", to-working-ir) + if contains(p,'X') or contains(p,'c') : do-stage("Resolve Kinds", resolve-kinds) + if contains(p,'X') or contains(p,'d') : do-stage("Make Explicit Reset", make-explicit-reset) + if contains(p,'X') or contains(p,'e') : do-stage("Infer Types", infer-types) + if contains(p,'X') or contains(p,'f') : do-stage("Resolve Genders", resolve-genders) + if contains(p,'X') or contains(p,'g') : do-stage("Expand Accessors", expand-accessors) + if contains(p,'X') or contains(p,'h') : do-stage("Lower To Ground", lower-to-ground) + if contains(p,'X') or contains(p,'i') : do-stage("Expand Indexed Connects", expand-connect-indexed) + if contains(p,'X') or contains(p,'j') : do-stage("Initialize Registers", initialize-registers) + if contains(p,'X') or contains(p,'k') : do-stage("Expand Whens", expand-whens) + if contains(p,'X') or contains(p,'l') : do-stage("Infer Widths", infer-widths) + if contains(p,'X') or contains(p,'m') : do-stage("Inline Instances", inline-instances) + if contains(p,'X') or contains(p,'n') : do-stage("Split Expressions", split-exp) + if contains(p,'X') or contains(p,'o') : do-stage("Real IR", to-real-ir) + if contains(p,'X') or contains(p,'F') : do-stage("To Flo", emit-flo{file,_}) + println("Done!") diff --git a/test/chisel3/BitsOps.fir b/test/chisel3/BitsOps.fir deleted file mode 100644 index 7e6c260d..00000000 --- a/test/chisel3/BitsOps.fir +++ /dev/null @@ -1,20 +0,0 @@ -;RUN: firrtl %s abcefghipjklmno cw | tee %s.out | FileCheck %s -;CHECK: To Flo -circuit BitsOps : - module BitsOps : - input b : UInt(16) - input a : UInt(16) - output notout : UInt(16) - output andout : UInt(16) - output orout : UInt(16) - output xorout : UInt(16) - - node T_13 = bit-not(a) - notout := T_13 - node T_14 = bit-and(a, b) - andout := T_14 - node T_15 = bit-or(a, b) - orout := T_15 - node T_16 = bit-xor(a, b) - xorout := T_16 -;CHECK: Finished To Flo diff --git a/test/chisel3/BundleWire.fir b/test/chisel3/BundleWire.fir deleted file mode 100644 index 86ffa4e8..00000000 --- a/test/chisel3/BundleWire.fir +++ /dev/null @@ -1,17 +0,0 @@ -;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s -;CHECK: To Flo -circuit BundleWire : - module BundleWire : - output in : {flip y : UInt(32), flip x : UInt(32)} - output outs : {y : UInt(32), x : UInt(32)}[4] - - wire coords : {y : UInt(32), x : UInt(32)}[4] - coords.0 := in - outs.0 := coords.0 - coords.1 := in - outs.1 := coords.1 - coords.2 := in - outs.2 := coords.2 - coords.3 := in - outs.3 := coords.3 -;CHECK: Finished To Flo diff --git a/test/chisel3/ComplexAssign.fir b/test/chisel3/ComplexAssign.fir deleted file mode 100644 index 14cb063c..00000000 --- a/test/chisel3/ComplexAssign.fir +++ /dev/null @@ -1,18 +0,0 @@ -;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s -;CHECK: To Flo -circuit ComplexAssign : - module ComplexAssign : - input in : {re : UInt(10), im : UInt(10)} - output out : {re : UInt(10), im : UInt(10)} - input e : UInt(1) - when e : - wire T_19 : {re : UInt(10), im : UInt(10)} - T_19 := in - out.re := T_19.re - out.im := T_19.im - else : - node T_20 = UInt(0, 1) - out.re := T_20 - node T_21 = UInt(0, 1) - out.im := T_21 -;CHECK: Finished To Flo diff --git a/test/chisel3/Counter.fir b/test/chisel3/Counter.fir deleted file mode 100644 index 55091d7f..00000000 --- a/test/chisel3/Counter.fir +++ /dev/null @@ -1,20 +0,0 @@ -;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s -;CHECK: To Flo -circuit Counter : - module Counter : - input inc : UInt(1) - output tot : UInt(8) - input amt : UInt(4) - - node T_13 = UInt(255, 8) - node T_14 = UInt(0, 8) - reg T_15 : UInt(8) - T_15.init := T_14 - when inc : - node T_16 = add-wrap(T_15, amt) - node T_17 = gt(T_16, T_13) - node T_18 = UInt(0, 1) - node T_19 = mux(T_17, T_18, T_16) - T_15 := T_19 - tot := T_15 -;CHECK: Finished To Flo diff --git a/test/chisel3/DirChange.fir b/test/chisel3/DirChange.fir deleted file mode 100644 index 4c26650f..00000000 --- a/test/chisel3/DirChange.fir +++ /dev/null @@ -1,10 +0,0 @@ -;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s -;CHECK: To Flo -circuit DirChange : - module DirChange : - input test1 : UInt(5) - output test2 : UInt(5) - input test3 : UInt(2)[10] - output test4 : {test41 : UInt(5), test42 : UInt(5)} - skip -;CHECK: Finished To Flo diff --git a/test/chisel3/EnableShiftRegister.fir b/test/chisel3/EnableShiftRegister.fir deleted file mode 100644 index 732e1dbc..00000000 --- a/test/chisel3/EnableShiftRegister.fir +++ /dev/null @@ -1,27 +0,0 @@ -;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s -;CHECK: To Flo -circuit EnableShiftRegister : - module EnableShiftRegister : - input in : UInt(4) - output out : UInt(4) - input shift : UInt(1) - - node T_14 = UInt(0, 4) - reg r0 : UInt(4) - r0.init := T_14 - node T_15 = UInt(0, 4) - reg r1 : UInt(4) - r1.init := T_15 - node T_16 = UInt(0, 4) - reg r2 : UInt(4) - r2.init := T_16 - node T_17 = UInt(0, 4) - reg r3 : UInt(4) - r3.init := T_17 - when shift : - r0 := in - r1 := r0 - r2 := r1 - r3 := r2 - out := r3 -;CHECK: Finished To Flo diff --git a/test/chisel3/GCD.fir b/test/chisel3/GCD.fir deleted file mode 100644 index 35da1802..00000000 --- a/test/chisel3/GCD.fir +++ /dev/null @@ -1,27 +0,0 @@ -;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s -;CHECK: To Flo -circuit GCD : - module GCD : - input b : UInt(16) - input a : UInt(16) - input e : UInt(1) - output z : UInt(16) - output v : UInt(1) - - reg x : UInt(16) - reg y : UInt(16) - node T_17 = gt(x, y) - when T_17 : - node T_18 = sub-wrap(x, y) - x := T_18 - else : - node T_19 = sub-wrap(y, x) - y := T_19 - when e : - x := a - y := b - z := x - node T_20 = UInt(0, 1) - node T_21 = equal(y, T_20) - v := T_21 -;CHECK: Finished To Flo diff --git a/test/chisel3/LFSR16.fir b/test/chisel3/LFSR16.fir index 7d1d6073..a8857882 100644 --- a/test/chisel3/LFSR16.fir +++ b/test/chisel3/LFSR16.fir @@ -1,20 +1,24 @@ +; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s +; CHECK: Done! + circuit LFSR16 : module LFSR16 : output out : UInt(16) input inc : UInt(1) - node T_16 : UInt(16) = UInt(1, 16) + node T_16 = UInt(1, 16) reg res : UInt(16) res.init := T_16 when inc : - node T_17 : UInt(1) = bit(res, 0) - node T_18 : UInt(1) = bit(res, 2) - node T_19 : UInt(1) = bit-xor(T_17, T_18) - node T_20 : UInt(1) = bit(res, 3) - node T_21 : UInt(1) = bit-xor(T_19, T_20) - node T_22 : UInt(1) = bit(res, 5) - node T_23 : UInt(1) = bit-xor(T_21, T_22) - node T_24 : UInt = bits(res, 15, 1) - node T_25 : UInt(1) = concat(T_23, T_24) + node T_17 = bit(res, 0) + node T_18 = bit(res, 2) + node T_19 = bit-xor(T_17, T_18) + node T_20 = bit(res, 3) + node T_21 = bit-xor(T_19, T_20) + node T_22 = bit(res, 5) + node T_23 = bit-xor(T_21, T_22) + node T_24 = bits(res, 15, 1) + node T_25 = cat(T_23, T_24) res := T_25 out := res + diff --git a/test/chisel3/MemorySearch.fir b/test/chisel3/MemorySearch.fir index 78e804d1..a2df4671 100644 --- a/test/chisel3/MemorySearch.fir +++ b/test/chisel3/MemorySearch.fir @@ -1,43 +1,45 @@ +; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s +; CHECK: Done! circuit MemorySearch : module MemorySearch : input target : UInt(4) output address : UInt(3) input en : UInt(1) - output done : UInt(1) + output odone : UInt(1) - node T_36 : UInt(3) = UInt(0, 3) + node T_35 = UInt(0, 3) reg index : UInt(3) - index.init := T_36 - node T_37 : UInt(1) = UInt(0, 1) - node T_38 : UInt(3) = UInt(4, 3) - node T_39 : UInt(4) = UInt(15, 4) - node T_40 : UInt(4) = UInt(14, 4) - node T_41 : UInt(2) = UInt(2, 2) - node T_42 : UInt(3) = UInt(5, 3) - node T_43 : UInt(4) = UInt(13, 4) + index.init := T_35 + node T_36 = UInt(0, 1) + node T_37 = UInt(4, 3) + node T_38 = UInt(15, 4) + node T_39 = UInt(14, 4) + node T_40 = UInt(2, 2) + node T_41 = UInt(5, 3) + node T_42 = UInt(13, 4) wire elts : UInt(1)[7] - elts.0 := T_37 - elts.1 := T_38 - elts.2 := T_39 - elts.3 := T_40 - elts.4 := T_41 - elts.5 := T_42 - elts.6 := T_43 + elts.0 := T_36 + elts.1 := T_37 + elts.2 := T_38 + elts.3 := T_39 + elts.4 := T_40 + elts.5 := T_41 + elts.6 := T_42 accessor elt = elts[index] - node T_44 : UInt(1) = bit-not(en) - node T_45 : UInt(1) = equal(elt, target) - node T_46 : UInt(3) = UInt(7, 3) - node T_47 : UInt(1) = equal(index, T_46) - node T_48 : UInt(1) = bit-or(T_45, T_47) - node done : UInt(1) = bit-and(T_44, T_48) + node T_43 = bit-not(en) + node T_44 = eq(elt, target) + node T_45 = UInt(7, 3) + node T_46 = eq(index, T_45) + node T_47 = bit-or(T_44, T_46) + node done = bit-and(T_43, T_47) when en : - node T_49 : UInt(1) = UInt(0, 1) - index := T_49 - else : - node T_50 : UInt(1) = bit-not(done) - when T_50 : - node T_51 : UInt(1) = UInt(1, 1) - node T_52 : UInt(3) = add(index, T_51) - index := T_52 - done := done + node T_48 = UInt(0, 1) + index := T_48 + else : + node T_49 = bit-not(done) + when T_49 : + node T_50 = UInt(1, 1) + node T_51 = add(index, T_50) + index := T_51 + odone := done address := index diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir deleted file mode 100644 index e4c526ec..00000000 --- a/test/chisel3/ModuleVec.fir +++ /dev/null @@ -1,25 +0,0 @@ -circuit ModuleVec : - module PlusOne : - input in : UInt(32) - output out : UInt(32) - - node T_34 : UInt(1) = UInt(1, 1) - node T_35 : UInt(32) = add(in, T_34) - out := T_35 - module PlusOne_26 : - input in : UInt(32) - output out : UInt(32) - - node T_36 : UInt(1) = UInt(1, 1) - node T_37 : UInt(32) = add(in, T_36) - out := T_37 - module ModuleVec : - input ins : UInt(32)[2] - output outs : UInt(32)[2] - - instance T_38 of PlusOne - instance T_39 of PlusOne_26 - pluses.0.in := ins.0 - outs.0 := pluses.0.out - pluses.1.in := ins.1 - outs.1 := pluses.1.out diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir index e41537e3..4f954465 100644 --- a/test/chisel3/Mul.fir +++ b/test/chisel3/Mul.fir @@ -1,44 +1,45 @@ +; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s +; CHECK: Done! circuit Mul : module Mul : input y : UInt(2) input x : UInt(2) output z : UInt(4) - node T_44 : UInt(4) = UInt(0, 4) - node T_45 : UInt(4) = UInt(0, 4) - node T_46 : UInt(4) = UInt(0, 4) - node T_47 : UInt(4) = UInt(0, 4) - node T_48 : UInt(4) = UInt(0, 4) - node T_49 : UInt(4) = UInt(1, 4) - node T_50 : UInt(4) = UInt(2, 4) - node T_51 : UInt(4) = UInt(3, 4) - node T_52 : UInt(4) = UInt(0, 4) - node T_53 : UInt(4) = UInt(2, 4) - node T_54 : UInt(4) = UInt(4, 4) - node T_55 : UInt(4) = UInt(6, 4) - node T_56 : UInt(4) = UInt(0, 4) - node T_57 : UInt(4) = UInt(3, 4) - node T_58 : UInt(4) = UInt(6, 4) - node T_59 : UInt(4) = UInt(9, 4) + node T_43 = UInt(0, 4) + node T_44 = UInt(0, 4) + node T_45 = UInt(0, 4) + node T_46 = UInt(0, 4) + node T_47 = UInt(0, 4) + node T_48 = UInt(1, 4) + node T_49 = UInt(2, 4) + node T_50 = UInt(3, 4) + node T_51 = UInt(0, 4) + node T_52 = UInt(2, 4) + node T_53 = UInt(4, 4) + node T_54 = UInt(6, 4) + node T_55 = UInt(0, 4) + node T_56 = UInt(3, 4) + node T_57 = UInt(6, 4) + node T_58 = UInt(9, 4) wire tbl : UInt(4)[16] - tbl.0 := T_44 - tbl.1 := T_45 - tbl.2 := T_46 - tbl.3 := T_47 - tbl.4 := T_48 - tbl.5 := T_49 - tbl.6 := T_50 - tbl.7 := T_51 - tbl.8 := T_52 - tbl.9 := T_53 - tbl.10 := T_54 - tbl.11 := T_55 - tbl.12 := T_56 - tbl.13 := T_57 - tbl.14 := T_58 - tbl.15 := T_59 - node T_60 : UInt(2) = UInt(2, 2) - node T_61 : UInt(2) = shift-left(x, T_60) - node T_62 : UInt(2) = bit-or(T_61, y) - accessor T_63 = tbl[T_62] - z := T_63 + tbl.0 := T_43 + tbl.1 := T_44 + tbl.2 := T_45 + tbl.3 := T_46 + tbl.4 := T_47 + tbl.5 := T_48 + tbl.6 := T_49 + tbl.7 := T_50 + tbl.8 := T_51 + tbl.9 := T_52 + tbl.10 := T_53 + tbl.11 := T_54 + tbl.12 := T_55 + tbl.13 := T_56 + tbl.14 := T_57 + tbl.15 := T_58 + node T_60 = shl(x, 2) + node T_61 = bit-or(T_60, y) + accessor T_62 = tbl[T_61] + z := T_62 diff --git a/test/chisel3/Outer.fir b/test/chisel3/Outer.fir index 0b808cb5..227c5dae 100644 --- a/test/chisel3/Outer.fir +++ b/test/chisel3/Outer.fir @@ -1,17 +1,19 @@ +; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s +; CHECK: Done! circuit Outer : module Inner : input in : UInt(8) output out : UInt(8) - node T_15 : UInt(1) = UInt(1, 1) - node T_16 : UInt(8) = add(in, T_15) - out := T_16 + node T_14 = UInt(1, 1) + node T_15 = add(in, T_14) + out := T_15 module Outer : input in : UInt(8) output out : UInt(8) - instance T_17 of Inner - T_17.in := in - node T_18 : UInt(2) = UInt(2, 2) - node T_19 : UInt(8) = times(T_17.out, T_18) - out := T_19 + inst T_16 of Inner + T_16.in := in + node T_17 = UInt(2, 2) + node T_18 = mul(T_16.out, T_17) + out := T_18 diff --git a/test/chisel3/RegisterVecShift.fir b/test/chisel3/RegisterVecShift.fir deleted file mode 100644 index 772c3d54..00000000 --- a/test/chisel3/RegisterVecShift.fir +++ /dev/null @@ -1,34 +0,0 @@ -circuit RegisterVecShift : - module RegisterVecShift : - input load : UInt(1) - output out : UInt(4) - input shift : UInt(1) - input ins : UInt(4)[4] - - reg delays : UInt(4)[4] - when reset : - node T_39 : UInt(4) = UInt(0, 4) - node T_40 : UInt(4) = UInt(0, 4) - node T_41 : UInt(4) = UInt(0, 4) - node T_42 : UInt(4) = UInt(0, 4) - wire T_43 : UInt(4)[4] - T_43.0 := T_39 - T_43.1 := T_40 - T_43.2 := T_41 - T_43.3 := T_42 - delays := T_43 - node T_44 : UInt(3) = UInt(5, 3) - node T_45 : UInt(3) = bit-and(T_44, load) - node T_46 : UInt(3) = UInt(4, 3) - node T_47 : UInt(1) = equal(T_45, T_46) - when T_47 : - delays.0 := ins.0 - delays.1 := ins.1 - delays.2 := ins.2 - delays.3 := ins.3 - else : when shift : - delays.0 := ins.0 - delays.1 := delays.0 - delays.2 := delays.1 - delays.3 := delays.2 - out := delays.3
\ No newline at end of file diff --git a/test/chisel3/Risc.fir b/test/chisel3/Risc.fir deleted file mode 100644 index 1a4d21e5..00000000 --- a/test/chisel3/Risc.fir +++ /dev/null @@ -1,66 +0,0 @@ -circuit Risc : - module Risc : - output out : UInt(32) - output valid : UInt(1) - input boot : UInt(1) - input isWr : UInt(1) - input wrAddr : UInt(8) - input wrData : UInt(32) - - mem file : UInt(32)[256] - mem code : UInt(32)[256] - node T_51 : UInt(8) = UInt(0, 8) - reg pc : UInt(8) - pc.init := T_51 - node add_op : UInt(1) = UInt(0, 1) - node imm_op : UInt(1) = UInt(1, 1) - accessor inst = code[pc] - node op : UInt = bits(inst, 31, 24) - node rci : UInt = bits(inst, 23, 16) - node rai : UInt = bits(inst, 15, 8) - node rbi : UInt = bits(inst, 7, 0) - node T_52 : UInt(1) = UInt(0, 1) - node T_53 : UInt(1) = equal(rai, T_52) - node T_54 : UInt(1) = UInt(0, 1) - accessor T_55 = file[rai] - node ra : UInt = multiplex(T_53, T_54, T_55) - node T_56 : UInt(1) = UInt(0, 1) - node T_57 : UInt(1) = equal(rbi, T_56) - node T_58 : UInt(1) = UInt(0, 1) - accessor T_59 = file[rbi] - node rb : UInt = multiplex(T_57, T_58, T_59) - wire rc : UInt(32) - node T_60 : UInt(1) = UInt(0, 1) - valid := T_60 - node T_61 : UInt(1) = UInt(0, 1) - out := T_61 - node T_62 : UInt(1) = UInt(0, 1) - rc := T_62 - when isWr : - accessor T_63 = code[wrAddr] - T_63 := wrData - else : when boot : - node T_64 : UInt(1) = UInt(0, 1) - pc := T_64 - else : - node T_65 : UInt(1) = equal(add_op, op) - when T_65 : - node T_66 : UInt = add-mod(ra, rb) - rc := T_66 - node T_67 : UInt(1) = equal(imm_op, op) - when T_67 : - node T_68 : UInt = shift-left(rai, 8) - node T_69 : UInt = bit-or(T_68, rbi) - rc := T_69 - out := rc - node T_70 : UInt(8) = UInt(255, 8) - node T_71 : UInt(1) = equal(rci, T_70) - when T_71 : - node T_72 : UInt(1) = UInt(1, 1) - valid := T_72 - else : - accessor T_73 = file[rci] - T_73 := rc - node T_74 : UInt(1) = UInt(1, 1) - node T_75 : UInt = add-mod(pc, T_74) - pc := T_75
\ No newline at end of file diff --git a/test/chisel3/Rom.fir b/test/chisel3/Rom.fir deleted file mode 100644 index bb4960a4..00000000 --- a/test/chisel3/Rom.fir +++ /dev/null @@ -1,24 +0,0 @@ -circuit Rom : - module Rom : - output out : UInt(8) - input addr : UInt(8) - - node T_24 : UInt(8) = UInt(0, 8) - node T_25 : UInt(8) = UInt(1, 8) - node T_26 : UInt(8) = UInt(2, 8) - node T_27 : UInt(8) = UInt(3, 8) - node T_28 : UInt(8) = UInt(4, 8) - node T_29 : UInt(8) = UInt(5, 8) - node T_30 : UInt(8) = UInt(6, 8) - node T_31 : UInt(8) = UInt(7, 8) - wire r : UInt(8)[8] - r.0 := T_24 - r.1 := T_25 - r.2 := T_26 - r.3 := T_27 - r.4 := T_28 - r.5 := T_29 - r.6 := T_30 - r.7 := T_31 - accessor T_32 = r[addr] - out := T_32
\ No newline at end of file diff --git a/test/chisel3/SIntOps.fir b/test/chisel3/SIntOps.fir deleted file mode 100644 index b026e1f3..00000000 --- a/test/chisel3/SIntOps.fir +++ /dev/null @@ -1,49 +0,0 @@ -circuit SIntOps : - module SIntOps : - input b : UInt(16) - input a : UInt(16) - output addout : UInt(16) - output subout : UInt(16) - output timesout : UInt(16) - output divout : UInt(16) - output modout : UInt(16) - output lshiftout : UInt(16) - output rshiftout : UInt(16) - output lessout : UInt(1) - output greatout : UInt(1) - output eqout : UInt(1) - output noteqout : UInt(1) - output lesseqout : UInt(1) - output greateqout : UInt(1) - output negout : UInt(16) - - node T_35 : UInt = add-mod(a, b) - addout := T_35 - node T_36 : UInt = sub-mod(a, b) - subout := T_36 - node T_37 : UInt = times(a, b) - node T_38 : UInt = bits(T_37, 15, 0) - timesout := T_38 - node T_39 : UInt = divide(a, b) - divout := T_39 - node T_40 : UInt = divide(a, b) - modout := T_40 - node T_41 : UInt = shift-left(a, 12) - node T_42 : UInt = bits(T_41, 15, 0) - lshiftout := T_42 - node T_43 : UInt = shift-right(a, 8) - rshiftout := T_43 - node T_44 : UInt(1) = less(a, b) - lessout := T_44 - node T_45 : UInt(1) = greater(a, b) - greatout := T_45 - node T_46 : UInt(1) = equal(a, b) - eqout := T_46 - node T_47 : UInt(1) = not-equal(a, b) - noteqout := T_47 - node T_48 : UInt(1) = less-eq(a, b) - lesseqout := T_48 - node T_49 : UInt(1) = greater-eq(a, b) - greateqout := T_49 - node T_50 : UInt = neg(a) - negout := T_50
\ No newline at end of file diff --git a/test/chisel3/Stack.fir b/test/chisel3/Stack.fir index 15596d0d..fbd198eb 100644 --- a/test/chisel3/Stack.fir +++ b/test/chisel3/Stack.fir @@ -1,3 +1,5 @@ +; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s +; CHECK: Done! circuit Stack : module Stack : input push : UInt(1) @@ -7,35 +9,35 @@ circuit Stack : input dataIn : UInt(32) mem stack_mem : UInt(32)[16] - node T_30 : UInt(5) = UInt(0, 5) + node T_30 = UInt(0, 5) reg sp : UInt(5) sp.init := T_30 - node T_31 : UInt(32) = UInt(0, 32) + node T_31 = UInt(0, 32) reg out : UInt(32) out.init := T_31 when en : - node T_32 : UInt(5) = UInt(16, 5) - node T_33 : UInt(1) = less(sp, T_32) - node T_34 : UInt(1) = bit-and(push, T_33) + node T_32 = UInt(16, 5) + node T_33 = lt(sp, T_32) + node T_34 = bit-and(push, T_33) when T_34 : accessor T_35 = stack_mem[sp] T_35 := dataIn - node T_36 : UInt(1) = UInt(1, 1) - node T_37 : UInt = add-mod(sp, T_36) + node T_36 = UInt(1, 1) + node T_37 = add-wrap(sp, T_36) sp := T_37 - else : - node T_38 : UInt(1) = UInt(0, 1) - node T_39 : UInt(1) = greater(sp, T_38) - node T_40 : UInt(1) = bit-and(pop, T_39) + else : + node T_38 = UInt(0, 1) + node T_39 = gt(sp, T_38) + node T_40 = bit-and(pop, T_39) when T_40 : - node T_41 : UInt(1) = UInt(1, 1) - node T_42 : UInt = sub-mod(sp, T_41) + node T_41 = UInt(1, 1) + node T_42 = sub-wrap(sp, T_41) sp := T_42 - node T_43 : UInt(1) = UInt(0, 1) - node T_44 : UInt(1) = greater(sp, T_43) + node T_43 = UInt(0, 1) + node T_44 = gt(sp, T_43) when T_44 : - node T_45 : UInt(1) = UInt(1, 1) - node T_46 : UInt = sub-mod(sp, T_45) + node T_45 = UInt(1, 1) + node T_46 = sub-wrap(sp, T_45) accessor T_47 = stack_mem[T_46] out := T_47 - dataOut := out
\ No newline at end of file + dataOut := out diff --git a/test/chisel3/Tbl.fir b/test/chisel3/Tbl.fir deleted file mode 100644 index 273047b0..00000000 --- a/test/chisel3/Tbl.fir +++ /dev/null @@ -1,16 +0,0 @@ -circuit Tbl : - module Tbl : - output o : UInt(16) - input i : UInt(16) - input d : UInt(16) - input we : UInt(1) - - mem m : UInt(10)[256] - node T_13 : UInt(1) = UInt(0, 1) - o := T_13 - when we : - accessor T_14 = m[i] - T_14 := d - else : - accessor T_15 = m[i] - o := T_15
\ No newline at end of file diff --git a/test/chisel3/UIntOps.fir b/test/chisel3/UIntOps.fir deleted file mode 100644 index 8d0e105e..00000000 --- a/test/chisel3/UIntOps.fir +++ /dev/null @@ -1,44 +0,0 @@ -circuit UIntOps : - module UIntOps : - input b : UInt(16) - input a : UInt(16) - output addout : UInt(16) - output subout : UInt(16) - output timesout : UInt(16) - output divout : UInt(16) - output modout : UInt(16) - output lshiftout : UInt(16) - output rshiftout : UInt(16) - output lessout : UInt(1) - output greatout : UInt(1) - output eqout : UInt(1) - output noteqout : UInt(1) - output lesseqout : UInt(1) - output greateqout : UInt(1) - - node T_32 : UInt(16) = add(a, b) - addout := T_32 - node T_33 : UInt(16) = sub(a, b) - subout := T_33 - node T_34 : UInt(16) = times(a, b) - timesout := T_34 - node T_35 : UInt(16) = divide(a, b) - divout := T_35 - node T_36 : UInt(16) = divide(a, b) - modout := T_36 - node T_37 : UInt(16) = shift-left(a, 12) - lshiftout := T_37 - node T_38 : UInt(16) = shift-right(a, 8) - rshiftout := T_38 - node T_39 : UInt(1) = less(a, b) - lessout := T_39 - node T_40 : UInt(1) = greater(a, b) - greatout := T_40 - node T_41 : UInt(1) = equal(a, b) - eqout := T_41 - node T_42 : UInt(1) = not-equal(a, b) - noteqout := T_42 - node T_43 : UInt(1) = less-eq(a, b) - lesseqout := T_43 - node T_44 : UInt(1) = greater-eq(a, b) - greateqout := T_44
\ No newline at end of file diff --git a/test/chisel3/VecApp.fir b/test/chisel3/VecApp.fir deleted file mode 100644 index 6b2bc21d..00000000 --- a/test/chisel3/VecApp.fir +++ /dev/null @@ -1,8 +0,0 @@ -circuit VecApp : - module VecApp : - input a : UInt(4) - input i : UInt(8)[4] - output d : UInt(8) - - accessor T_13 = i[a] - d := T_13
\ No newline at end of file diff --git a/test/chisel3/VecShiftRegister.fir b/test/chisel3/VecShiftRegister.fir deleted file mode 100644 index 86f20796..00000000 --- a/test/chisel3/VecShiftRegister.fir +++ /dev/null @@ -1,19 +0,0 @@ -circuit VecShiftRegister : - module VecShiftRegister : - input load : UInt(1) - output out : UInt(4) - input shift : UInt(1) - input ins : UInt(4)[4] - - reg delays : UInt(4)[4] - when load : - delays.0 := ins.0 - delays.1 := ins.1 - delays.2 := ins.2 - delays.3 := ins.3 - else : when shift : - delays.0 := ins.0 - delays.1 := delays.0 - delays.2 := delays.1 - delays.3 := delays.2 - out := delays.3
\ No newline at end of file diff --git a/test/chisel3/VendingMachine.fir b/test/chisel3/VendingMachine.fir deleted file mode 100644 index 4ae94524..00000000 --- a/test/chisel3/VendingMachine.fir +++ /dev/null @@ -1,46 +0,0 @@ -circuit VendingMachine : - module VendingMachine : - output valid : UInt(1) - input nickel : UInt(1) - input dime : UInt(1) - - node T_34 : UInt(3) = UInt(5, 3) - wire c : UInt - c := T_34 - node T_35 : UInt(3) = UInt(0, 3) - wire sIdle : UInt - sIdle := T_35 - node T_36 : UInt(3) = UInt(1, 3) - wire s5 : UInt - s5 := T_36 - node T_37 : UInt(3) = UInt(2, 3) - wire s10 : UInt - s10 := T_37 - node T_38 : UInt(3) = UInt(3, 3) - wire s15 : UInt - s15 := T_38 - node T_39 : UInt(3) = UInt(4, 3) - wire sOk : UInt - sOk := T_39 - reg state : UInt - state.init := sIdle - node T_40 : UInt(1) = equal(state, sIdle) - when T_40 : - when nickel : state := s5 - when dime : state := s10 - node T_41 : UInt(1) = equal(state, s5) - when T_41 : - when nickel : state := s10 - when dime : state := s15 - node T_42 : UInt(1) = equal(state, s10) - when T_42 : - when nickel : state := s15 - when dime : state := sOk - node T_43 : UInt(1) = equal(state, s15) - when T_43 : - when nickel : state := sOk - when dime : state := sOk - node T_44 : UInt(1) = equal(state, sOk) - when T_44 : state := sIdle - node T_45 : UInt(1) = equal(state, sOk) - valid := T_45
\ No newline at end of file diff --git a/test/hello.fir b/test/hello.fir deleted file mode 100644 index 4a905ab9..00000000 --- a/test/hello.fir +++ /dev/null @@ -1,2 +0,0 @@ -# RUN: echo hello | FileCheck %s -# CHECK: hello diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir index 01257279..96bf8d54 100644 --- a/test/passes/expand-accessors/accessor-mem.fir +++ b/test/passes/expand-accessors/accessor-mem.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcdefg c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefg -p c | tee %s.out | FileCheck %s ;CHECK: Expand Accessors circuit top : diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir index 599abb8f..2c6bbd5f 100644 --- a/test/passes/expand-accessors/accessor-vec.fir +++ b/test/passes/expand-accessors/accessor-vec.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcdefg c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefg -p c | tee %s.out | FileCheck %s ;CHECK: Expand Accessors circuit top : diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir index e00dd9c2..4e6f3456 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcdefghi c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefghi -p c | tee %s.out | FileCheck %s ; CHECK: Expand Indexed Connects circuit top : diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir index c62a36c6..45ae938b 100644 --- a/test/passes/expand-whens/one-when.fir +++ b/test/passes/expand-whens/one-when.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcefghipj c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefghijk -p c | tee %s.out | FileCheck %s ; CHECK: Expand Whens circuit top : diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir index b1da7410..653dfb2d 100644 --- a/test/passes/expand-whens/partial-init.fir +++ b/test/passes/expand-whens/partial-init.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcefghipj c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefghijk -p c | tee %s.out | FileCheck %s ; CHECK: Expand Whens circuit top : diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir index 09225143..c2814038 100644 --- a/test/passes/expand-whens/two-when.fir +++ b/test/passes/expand-whens/two-when.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcdefghijkp c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefghijk -p c | tee %s.out | FileCheck %s ; CHECK: Expand Whens circuit top : diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir index d9b86115..c3d4896a 100644 --- a/test/passes/infer-types/bundle.fir +++ b/test/passes/infer-types/bundle.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcde ct | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcde -p ct | tee %s.out | FileCheck %s ;CHECK: Infer Types circuit top : diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir index aa43644c..300101ad 100644 --- a/test/passes/infer-types/gcd.fir +++ b/test/passes/infer-types/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcde ct | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcde -p ct | tee %s.out | FileCheck %s ;CHECK: Infer Types circuit top : diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index 2c37f361..35634a6f 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcde ct | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcde -p ct | tee %s.out | FileCheck %s ;CHECK: Infer Types circuit top : diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir index f9f7ac5c..a550326b 100644 --- a/test/passes/infer-widths/gcd.fir +++ b/test/passes/infer-widths/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcefghipjk cT | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cT | tee %s.out | FileCheck %s ;CHECK: Infer Widths circuit top : diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir index fcd08ac6..432030d5 100644 --- a/test/passes/infer-widths/simple.fir +++ b/test/passes/infer-widths/simple.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcefghipjk cT | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cT | tee %s.out | FileCheck %s ;CHECK: Infer Widths circuit top : diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir index 5713cd43..8cb856f2 100644 --- a/test/passes/inline/gcd.fir +++ b/test/passes/inline/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcefghipjkl c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefghijklm -p c | tee %s.out | FileCheck %s ;CHECK: Inline Instances circuit top : diff --git a/test/passes/jacktest/bundlewire.fir b/test/passes/jacktest/bundlewire.fir index 18e246a9..cd5b2dfe 100644 --- a/test/passes/jacktest/bundlewire.fir +++ b/test/passes/jacktest/bundlewire.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcefghipj cg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x X -p cg | tee %s.out | FileCheck %s ; CHECK: Expand Whens diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir index a05ef6e6..92c6eb46 100644 --- a/test/passes/jacktest/gcd.fir +++ b/test/passes/jacktest/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcefghipjklmnoq cw | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x X -p cw | tee %s.out | FileCheck %s ;CHECK: To Flo circuit GCD : diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir index 8422b50d..a7d35bf6 100644 --- a/test/passes/jacktest/risc.fir +++ b/test/passes/jacktest/risc.fir @@ -1,5 +1,6 @@ -; RUN: firrtl %s qabcdefghijklmnopj c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s ; CHECK: Expand Whens + circuit Risc : module Risc : output out : UInt(32) diff --git a/test/passes/jacktest/testlower.fir b/test/passes/jacktest/testlower.fir index 0356597e..c338d094 100644 --- a/test/passes/jacktest/testlower.fir +++ b/test/passes/jacktest/testlower.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcefghipj cg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s ; CHECK: Expand Whens diff --git a/test/passes/jacktest/vecshift.fir b/test/passes/jacktest/vecshift.fir index 9910064d..4d2563af 100644 --- a/test/passes/jacktest/vecshift.fir +++ b/test/passes/jacktest/vecshift.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcefghipj c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s ; CHECK: Expand Whens diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir index 8c12137f..0ebbb13d 100644 --- a/test/passes/lower-to-ground/accessor.fir +++ b/test/passes/lower-to-ground/accessor.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcdefgh c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s ; CHECK: Lower To Ground circuit top : diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index f1b25854..77de74db 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcdefgh c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s ; CHECK: Lower To Ground circuit top : diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir index 2947eb8f..859ddb47 100644 --- a/test/passes/lower-to-ground/bundle.fir +++ b/test/passes/lower-to-ground/bundle.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcdefgh c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s circuit top : module m : diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir index 4ab3ba9b..0b14c187 100644 --- a/test/passes/lower-to-ground/nested-vec.fir +++ b/test/passes/lower-to-ground/nested-vec.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcdefgh c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s ; CHECK: Lower To Ground circuit top : diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir index 219996fb..23ac8ac3 100644 --- a/test/passes/lower-to-ground/register.fir +++ b/test/passes/lower-to-ground/register.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcdefghi c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s ; CHECK: Lower To Ground circuit top : diff --git a/test/passes/make-explicit-reset/mix-reset.fir b/test/passes/make-explicit-reset/mix-reset.fir index c6487c8d..2f740fa2 100644 --- a/test/passes/make-explicit-reset/mix-reset.fir +++ b/test/passes/make-explicit-reset/mix-reset.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abc c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcd -p c | tee %s.out | FileCheck %s ; CHECK: Make Explicit Reset circuit top : diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir index c6e2a905..931372cb 100644 --- a/test/passes/resolve-genders/accessor.fir +++ b/test/passes/resolve-genders/accessor.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcdef cg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdef -p cg | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : diff --git a/test/passes/resolve-genders/bigenders.fir b/test/passes/resolve-genders/bigenders.fir index 2a66062f..48987a9a 100644 --- a/test/passes/resolve-genders/bigenders.fir +++ b/test/passes/resolve-genders/bigenders.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcdefghipj c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : diff --git a/test/passes/resolve-genders/bulk.fir b/test/passes/resolve-genders/bulk.fir index ab549975..491760b6 100644 --- a/test/passes/resolve-genders/bulk.fir +++ b/test/passes/resolve-genders/bulk.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcdef cg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir index 2190d284..44e0200f 100644 --- a/test/passes/resolve-genders/gcd.fir +++ b/test/passes/resolve-genders/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcef cg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdef -p cg | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir index d790272c..c1708631 100644 --- a/test/passes/resolve-genders/ports.fir +++ b/test/passes/resolve-genders/ports.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcdef cg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdef -p cg | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir index 247251ae..77cf13b3 100644 --- a/test/passes/resolve-genders/subbundle.fir +++ b/test/passes/resolve-genders/subbundle.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcdefghipj c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s ;CHECK: Lower To Ground circuit top : diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir index e7cd8f34..e1a05236 100644 --- a/test/passes/resolve-kinds/gcd.fir +++ b/test/passes/resolve-kinds/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s ab ck | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abc -p ck | tee %s.out | FileCheck %s ; CHECK: Resolve Kinds circuit top : diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir index a5278efd..75efa2f8 100644 --- a/test/passes/split-exp/gcd.fir +++ b/test/passes/split-exp/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcefghipjklm c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x abcdefghijklmn -p c | tee %s.out | FileCheck %s ;CHECK: Split Expressions circuit top : diff --git a/test/passes/to-flo/gcd.fir b/test/passes/to-flo/gcd.fir index ea316bed..9ea5d7b1 100644 --- a/test/passes/to-flo/gcd.fir +++ b/test/passes/to-flo/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl %s abcefghipjklmno cw | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s ;CHECK: Flo circuit top : diff --git a/test/simple.fir b/test/simple.fir deleted file mode 100644 index d00f8f7a..00000000 --- a/test/simple.fir +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: firrtl %s ab | tee %s.out | FileCheck %s - -circuit top : - module subtracter : - input x : UInt - input y : UInt - output z : UInt - z := sub-mod(x, y) -; CHECK: output z : UInt -; CHECK: port:z := sub-mod(port:x, port:y) - |