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; RUN: firrtl %s abcdefghipj c | tee %s.out | FileCheck %s
;CHECK: Resolve Genders
circuit top :
module M :
input i : UInt(10)
output o : UInt(10)
wire w : {x : UInt(10), flip y : UInt(10)}
w.x := i
w.y := i
o := w.x
o := w.y
; CHECK: Finished Resolve Genders
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