diff options
| author | azidar | 2015-04-28 17:32:19 -0700 |
|---|---|---|
| committer | azidar | 2015-04-28 17:32:19 -0700 |
| commit | 1644ed195522cd7343aaaa047e6669529907de9f (patch) | |
| tree | 250d34e3bf5616e01b4629ee6497cdd1ce9647b8 /test/chisel3/ModuleVec.fir | |
| parent | d6d630e6dbe3e5dd3c335cc8bd65a81d9dcb0f5f (diff) | |
Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec.fir doesn't work because incorrecly generated?
Diffstat (limited to 'test/chisel3/ModuleVec.fir')
| -rw-r--r-- | test/chisel3/ModuleVec.fir | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir index 7198667a..7379024b 100644 --- a/test/chisel3/ModuleVec.fir +++ b/test/chisel3/ModuleVec.fir @@ -2,29 +2,29 @@ ; CHECK: Done! circuit ModuleVec : module PlusOne : - input in : UInt(32) - output out : UInt(32) + input in : UInt<32> + output out : UInt<32> - node T_33 = UInt(1, 1) + node T_33 = UInt<1>(1) node T_34 = add(in, T_33) out := T_34 module PlusOne_25 : - input in : UInt(32) - output out : UInt(32) + input in : UInt<32> + output out : UInt<32> - node T_35 = UInt(1, 1) + node T_35 = UInt<1>(1) node T_36 = add(in, T_35) out := T_36 module ModuleVec : - output ins : UInt(32)[2] - output outs : UInt(32)[2] + output ins : UInt<32>[2] + output outs : UInt<32>[2] inst T_37 of PlusOne inst T_38 of PlusOne_25 - wire pluses : {flip in : UInt(32), out : UInt(32)}[2] - pluses.0 := T_37 - pluses.1 := T_38 + wire pluses : {flip in : UInt<32>, out : UInt<32>}[2] + pluses[0] := T_37 + pluses[1] := T_38 pluses.s.in := ins.s - outs.0 := pluses.s.out - pluses.s.in := ins.1 - outs.1 := pluses.1.out + outs[0] := pluses.s.out + pluses.s.in := ins[1] + outs[1] := pluses[1].out |