From 1644ed195522cd7343aaaa047e6669529907de9f Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 28 Apr 2015 17:32:19 -0700
Subject: Instances are now male. Reworked lowering pass to be sane.
 chisel3/ModuleVec.fir doesn't work because incorrecly generated?

---
 test/chisel3/ModuleVec.fir | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

(limited to 'test/chisel3/ModuleVec.fir')

diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
index 7198667a..7379024b 100644
--- a/test/chisel3/ModuleVec.fir
+++ b/test/chisel3/ModuleVec.fir
@@ -2,29 +2,29 @@
 ; CHECK: Done!
 circuit ModuleVec : 
   module PlusOne : 
-    input in : UInt(32)
-    output out : UInt(32)
+    input in : UInt<32>
+    output out : UInt<32>
     
-    node T_33 = UInt(1, 1)
+    node T_33 = UInt<1>(1)
     node T_34 = add(in, T_33)
     out := T_34
   module PlusOne_25 : 
-    input in : UInt(32)
-    output out : UInt(32)
+    input in : UInt<32>
+    output out : UInt<32>
     
-    node T_35 = UInt(1, 1)
+    node T_35 = UInt<1>(1)
     node T_36 = add(in, T_35)
     out := T_36
   module ModuleVec : 
-    output ins : UInt(32)[2]
-    output outs : UInt(32)[2]
+    output ins : UInt<32>[2]
+    output outs : UInt<32>[2]
     
     inst T_37 of PlusOne
     inst T_38 of PlusOne_25
-    wire pluses : {flip in : UInt(32), out : UInt(32)}[2]
-    pluses.0 := T_37
-    pluses.1 := T_38
+    wire pluses : {flip in : UInt<32>, out : UInt<32>}[2]
+    pluses[0] := T_37
+    pluses[1] := T_38
     pluses.s.in := ins.s
-    outs.0 := pluses.s.out
-    pluses.s.in := ins.1
-    outs.1 := pluses.1.out
+    outs[0] := pluses.s.out
+    pluses.s.in := ins[1]
+    outs[1] := pluses[1].out
-- 
cgit v1.2.3