diff options
| author | azidar | 2015-04-16 17:05:46 -0700 |
|---|---|---|
| committer | azidar | 2015-04-16 17:05:46 -0700 |
| commit | 06ff7f7dddcb479d9d4d775a55cbb18d873b35b9 (patch) | |
| tree | 5023aa9aa4e944d9b3911a8dddf43ece6f6f1455 /test/chisel3/ModuleVec.fir | |
| parent | 5dfc741fd04c7fa357b976b57086d67244d3d22a (diff) | |
Updated parser to correctly read empty statements
Diffstat (limited to 'test/chisel3/ModuleVec.fir')
| -rw-r--r-- | test/chisel3/ModuleVec.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir index 1372d1f6..e4c526ec 100644 --- a/test/chisel3/ModuleVec.fir +++ b/test/chisel3/ModuleVec.fir @@ -22,4 +22,4 @@ circuit ModuleVec : pluses.0.in := ins.0 outs.0 := pluses.0.out pluses.1.in := ins.1 - outs.1 := pluses.1.out
\ No newline at end of file + outs.1 := pluses.1.out |