Updated parser to correctly read empty statements

12 files changed, 61 insertions, 40 deletions

diff --git a/test/chisel3/BitsOps.fir b/test/chisel3/BitsOps.fir
index 5fa56b60..7e6c260d 100644
--- a/test/chisel3/BitsOps.fir
+++ b/test/chisel3/BitsOps.fir
@@ -1,3 +1,5 @@
+;RUN: firrtl %s abcefghipjklmno cw | tee %s.out | FileCheck %s
+;CHECK: To Flo
 circuit BitsOps : 
   module BitsOps : 
     input b : UInt(16)
@@ -7,11 +9,12 @@ circuit BitsOps :
     output orout : UInt(16)
     output xorout : UInt(16)
     
-    node T_13 : UInt = bit-not(a)
+    node T_13 = bit-not(a)
     notout := T_13
-    node T_14 : UInt = bit-and(a, b)
+    node T_14 = bit-and(a, b)
     andout := T_14
-    node T_15 : UInt = bit-or(a, b)
+    node T_15 = bit-or(a, b)
     orout := T_15
-    node T_16 : UInt = bit-xor(a, b)
-    xorout := T_16
\ No newline at end of file
+    node T_16 = bit-xor(a, b)
+    xorout := T_16
+;CHECK: Finished To Flo
diff --git a/test/chisel3/BundleWire.fir b/test/chisel3/BundleWire.fir
index 72d3061e..86ffa4e8 100644
--- a/test/chisel3/BundleWire.fir
+++ b/test/chisel3/BundleWire.fir
@@ -1,9 +1,11 @@
+;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s
+;CHECK: To Flo
 circuit BundleWire : 
   module BundleWire : 
-    output in : {input y : UInt(32), input x : UInt(32)}
-    output outs : {output y : UInt(32), output x : UInt(32)}[4]
+    output in : {flip y : UInt(32), flip x : UInt(32)}
+    output outs : {y : UInt(32), x : UInt(32)}[4]
     
-    wire coords : {output y : UInt(32), output x : UInt(32)}[4]
+    wire coords : {y : UInt(32), x : UInt(32)}[4]
     coords.0 := in
     outs.0 := coords.0
     coords.1 := in
@@ -11,4 +13,5 @@ circuit BundleWire :
     coords.2 := in
     outs.2 := coords.2
     coords.3 := in
-    outs.3 := coords.3
\ No newline at end of file
+    outs.3 := coords.3
+;CHECK: Finished To Flo
diff --git a/test/chisel3/ComplexAssign.fir b/test/chisel3/ComplexAssign.fir
index 2cf52370..14cb063c 100644
--- a/test/chisel3/ComplexAssign.fir
+++ b/test/chisel3/ComplexAssign.fir
@@ -1,15 +1,18 @@
+;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s
+;CHECK: To Flo
 circuit ComplexAssign : 
   module ComplexAssign : 
-    input in : {output re : UInt(10), output im : UInt(10)}
-    output out : {output re : UInt(10), output im : UInt(10)}
+    input in : {re : UInt(10), im : UInt(10)}
+    output out : {re : UInt(10), im : UInt(10)}
     input e : UInt(1)
     when e : 
-      wire T_19 : {output re : UInt(10), output im : UInt(10)}
+      wire T_19 : {re : UInt(10), im : UInt(10)}
       T_19 := in
       out.re := T_19.re
       out.im := T_19.im
      else : 
-      node T_20 : UInt(1) = UInt(0, 1)
+      node T_20 = UInt(0, 1)
       out.re := T_20
-      node T_21 : UInt(1) = UInt(0, 1)
-      out.im := T_21
\ No newline at end of file
+      node T_21 = UInt(0, 1)
+      out.im := T_21
+;CHECK: Finished To Flo
diff --git a/test/chisel3/Counter.fir b/test/chisel3/Counter.fir
index 8bab249c..55091d7f 100644
--- a/test/chisel3/Counter.fir
+++ b/test/chisel3/Counter.fir
@@ -1,17 +1,20 @@
+;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s
+;CHECK: To Flo
 circuit Counter : 
   module Counter : 
     input inc : UInt(1)
     output tot : UInt(8)
     input amt : UInt(4)
     
-    node T_13 : UInt(8) = UInt(255, 8)
-    node T_14 : UInt(8) = UInt(0, 8)
+    node T_13 = UInt(255, 8)
+    node T_14 = UInt(0, 8)
     reg T_15 : UInt(8)
     T_15.init := T_14
     when inc : 
-      node T_16 : UInt = add-mod(T_15, amt)
-      node T_17 : UInt(1) = greater(T_16, T_13)
-      node T_18 : UInt(1) = UInt(0, 1)
-      node T_19 : UInt(1) = multiplex(T_17, T_18, T_16)
+      node T_16 = add-wrap(T_15, amt)
+      node T_17 = gt(T_16, T_13)
+      node T_18 = UInt(0, 1)
+      node T_19 = mux(T_17, T_18, T_16)
       T_15 := T_19
-    tot := T_15
\ No newline at end of file
+    tot := T_15
+;CHECK: Finished To Flo
diff --git a/test/chisel3/DirChange.fir b/test/chisel3/DirChange.fir
index c948dc85..4c26650f 100644
--- a/test/chisel3/DirChange.fir
+++ b/test/chisel3/DirChange.fir
@@ -1,7 +1,10 @@
+;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s
+;CHECK: To Flo
 circuit DirChange : 
   module DirChange : 
     input test1 : UInt(5)
     output test2 : UInt(5)
     input test3 : UInt(2)[10]
-    output test4 : {output test41 : UInt(5), output test42 : UInt(5)}
-    skip
\ No newline at end of file
+    output test4 : {test41 : UInt(5), test42 : UInt(5)}
+    skip
+;CHECK: Finished To Flo
diff --git a/test/chisel3/EnableShiftRegister.fir b/test/chisel3/EnableShiftRegister.fir
index aa7d36ae..732e1dbc 100644
--- a/test/chisel3/EnableShiftRegister.fir
+++ b/test/chisel3/EnableShiftRegister.fir
@@ -1,19 +1,21 @@
+;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s
+;CHECK: To Flo
 circuit EnableShiftRegister : 
   module EnableShiftRegister : 
     input in : UInt(4)
     output out : UInt(4)
     input shift : UInt(1)
     
-    node T_14 : UInt(4) = UInt(0, 4)
+    node T_14 = UInt(0, 4)
     reg r0 : UInt(4)
     r0.init := T_14
-    node T_15 : UInt(4) = UInt(0, 4)
+    node T_15 = UInt(0, 4)
     reg r1 : UInt(4)
     r1.init := T_15
-    node T_16 : UInt(4) = UInt(0, 4)
+    node T_16 = UInt(0, 4)
     reg r2 : UInt(4)
     r2.init := T_16
-    node T_17 : UInt(4) = UInt(0, 4)
+    node T_17 = UInt(0, 4)
     reg r3 : UInt(4)
     r3.init := T_17
     when shift : 
@@ -21,4 +23,5 @@ circuit EnableShiftRegister :
       r1 := r0
       r2 := r1
       r3 := r2
-    out := r3
\ No newline at end of file
+    out := r3
+;CHECK: Finished To Flo
diff --git a/test/chisel3/GCD.fir b/test/chisel3/GCD.fir
index 5b103a6b..35da1802 100644
--- a/test/chisel3/GCD.fir
+++ b/test/chisel3/GCD.fir
@@ -1,3 +1,5 @@
+;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s
+;CHECK: To Flo
 circuit GCD : 
   module GCD : 
     input b : UInt(16)
@@ -8,17 +10,18 @@ circuit GCD :
     
     reg x : UInt(16)
     reg y : UInt(16)
-    node T_17 : UInt(1) = greater(x, y)
+    node T_17 = gt(x, y)
     when T_17 : 
-      node T_18 : UInt = sub-mod(x, y)
+      node T_18 = sub-wrap(x, y)
       x := T_18
      else : 
-      node T_19 : UInt = sub-mod(y, x)
+      node T_19 = sub-wrap(y, x)
       y := T_19
     when e : 
       x := a
       y := b
     z := x
-    node T_20 : UInt(1) = UInt(0, 1)
-    node T_21 : UInt(1) = equal(y, T_20)
-    v := T_21
\ No newline at end of file
+    node T_20 = UInt(0, 1)
+    node T_21 = equal(y, T_20)
+    v := T_21
+;CHECK: Finished To Flo
diff --git a/test/chisel3/LFSR16.fir b/test/chisel3/LFSR16.fir
index 7e661548..7d1d6073 100644
--- a/test/chisel3/LFSR16.fir
+++ b/test/chisel3/LFSR16.fir
@@ -17,4 +17,4 @@ circuit LFSR16 :
       node T_24 : UInt = bits(res, 15, 1)
       node T_25 : UInt(1) = concat(T_23, T_24)
       res := T_25
-    out := res
\ No newline at end of file
+    out := res
diff --git a/test/chisel3/MemorySearch.fir b/test/chisel3/MemorySearch.fir
index f7a0fb84..78e804d1 100644
--- a/test/chisel3/MemorySearch.fir
+++ b/test/chisel3/MemorySearch.fir
@@ -40,4 +40,4 @@ circuit MemorySearch :
         node T_52 : UInt(3) = add(index, T_51)
         index := T_52
     done := done
-    address := index
\ No newline at end of file
+    address := index
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
index 1372d1f6..e4c526ec 100644
--- a/test/chisel3/ModuleVec.fir
+++ b/test/chisel3/ModuleVec.fir
@@ -22,4 +22,4 @@ circuit ModuleVec :
     pluses.0.in := ins.0
     outs.0 := pluses.0.out
     pluses.1.in := ins.1
-    outs.1 := pluses.1.out
\ No newline at end of file
+    outs.1 := pluses.1.out
diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir
index f8ba0b78..e41537e3 100644
--- a/test/chisel3/Mul.fir
+++ b/test/chisel3/Mul.fir
@@ -41,4 +41,4 @@ circuit Mul :
     node T_61 : UInt(2) = shift-left(x, T_60)
     node T_62 : UInt(2) = bit-or(T_61, y)
     accessor T_63 = tbl[T_62]
-    z := T_63
\ No newline at end of file
+    z := T_63
diff --git a/test/chisel3/Outer.fir b/test/chisel3/Outer.fir
index e3a67a6e..0b808cb5 100644
--- a/test/chisel3/Outer.fir
+++ b/test/chisel3/Outer.fir
@@ -14,4 +14,4 @@ circuit Outer :
     T_17.in := in
     node T_18 : UInt(2) = UInt(2, 2)
     node T_19 : UInt(8) = times(T_17.out, T_18)
-    out := T_19
\ No newline at end of file
+    out := T_19