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Since InstanceGraph now has all modules in its graph, test ConstProp on all modules as a default behaviour.
- Need to think about how to target ConstProp only for a specific module?
Close #644
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hierarchy
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* Added option to emit final annotations
* Removed extra > from output-anno-file
* Removed other extra > from input-anno-file
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* Reorder port and wire assignments in Verilog
* Fixed up syntax
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instantiated multiple times (#634)
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* initial implementation of InlineDeepTransformation
* rewrote transformation to not have any side effects in terms on inlining that was not annotated to be inlined
* minor rewrites
* renamed transformations to Flatten
* fixes according to review
* added more comments and fixed formating/style
* fixed spacing, minor style fixes
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Fixes issue in https://github.com/freechipsproject/rocket-chip/pull/848
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* Fixed inability to disable combo loop check
Moved checking of dontCheckComboLoops into loadAnnotations so
that it works in cases where Driver.execute is not used.
* Fix test for annotations, modifications to loadAnnotations
made 2 more annotations visible.
* Remove debug println from DriverSpec
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Names that do not start with '_' are "better" than those that do
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Constant Propagation will not optimize across components marked
dontTouch
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This makes it more concise to write tests
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Gives all transform specs access to useful utilities (like dontTouch).
Deletes some duplicate code. Parsing mode UseInfo is fine for
everything, only matters if the test actually uses info.
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Fixes bug where the Verilog emitter could pull the next value for a
register that feeds a second register, removing the first register from
the second register's update.
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This requires a quick second pass to back propagate constant wires but
the QoR win is substantial. We also only need to count back propagations
in determining whether to run ConstProp again which shaves off an
iteration in the common case.
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Similar to #543
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Also add tests for what should happen to 'is invalid' in ExpandWhens
Fixes #606
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Resolves #600
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* Display the total time firrtl took to compile
* Switch timing print out to error(aka default)
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Makes Verilog more readable to both humans and scripts
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* Update dependencies and JavaConverters for Scala 2.12
* Bump Scala (and library) version(s).
* replace "error" with "Utils.error"; bump Scala version to 2.11.11
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We walked the whole set of vertices for every dont touch
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We were recursing on Types of Expressions which not only is super inefficient
(especially since we are already calling InferTypes afterward), but also
duplicates each of the Type objects that need changing.
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#504 (#551)
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* Upgrade Logging facility
Make thread-safe
Make logging by package name work
Use caching of class names to level for performance
Make some tests to show this working
* quick fix for dynamic logging variable
* A number of changes based on Adam's suggestions
Default LoggerState
But there is an invoke method now to handle threading issues. This should be propagated to other
projects Driver.execute methods
* Add built-in support for string capture of Logging
* Usability fixes for logging stuff. Settings made to the logger prior to execute/invoke will be passed along if possible.
* A couple style fixes
Comment and privatize Logger state
* Name and save string buffers used for logging
* Fix default logging state setting
Fix logging test, did not have change to command argument
* comment out logging in InlineInstanceTests
* Changed invoke to makeScope
Nested makeScopes share same state object
Removed earlier named string buffer implementation
* Better name for captor get data
* Add trace tests to make sure it works too
* Fix call into logger settings
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Fixes #589
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* Bugfix: pad is max(width,const) during constprop
* Fixed max syntax
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Performs DCE by constructing a global dependency graph starting with top-level
outputs, external module ports, and simulation constructs as circuit sinks.
External modules can optionally be eligible for DCE via the
OptimizableExtModuleAnnotation.
Dead code is eliminated across module boundaries. Wires, ports, registers, and
memories are all eligible for removal. Components marked with a
DontTouchAnnotation will be treated as a circuit sink and thus anything that
drives such a marked component will NOT be removed.
This transform preserves deduplication. All instances of a given DefModule are
treated as the same individual module. Thus, while certain instances may have
dead code due to the circumstances of their instantiation in their parent
module, they will still not be removed. To remove such modules, use the
NoDedupAnnotation to prevent deduplication.
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Now you should be able to copy paste the example code :)
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* Added pass name to debug logger
* Addresses #459. Rewords transform annotations API.
Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.
* Added more stylized debugging style
* WIP: make pass transform
* WIP: All tests pass, need to pull master
* Cleaned up PR
* Added rename updates to all core transforms
* Added more rename tests, and bugfixes
* Renaming tracks non-leaf subfields
E.g. given:
wire x: {a: UInt<1>, b: UInt<1>[2]}
Annotating x.b will eventually annotate x_b_0 and x_b_1
* Bugfix instance rename lowering broken
* Address review comments
* Remove check for seqTransform, UnknownForm too restrictive check
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Remove infix notation on calls with side effects.
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