aboutsummaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorDonggyu Kim2017-07-17 11:48:11 -0700
committerJack2017-07-17 14:23:57 -0700
commit97642d6ddeca4e2109010ac5d6a0a199df01f28c (patch)
tree76de155cd5314bdee2cbac07066d829c85a63b6d /src
parent427095ad97ac31e994fee3d083eb18f78e701004 (diff)
do not swap wire names with node names
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/transforms/ConstantPropagation.scala2
-rw-r--r--src/test/scala/firrtlTests/ConstantPropagationTests.scala30
2 files changed, 31 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/ConstantPropagation.scala b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
index 46c12b2d..d5a4b7e1 100644
--- a/src/main/scala/firrtl/transforms/ConstantPropagation.scala
+++ b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
@@ -317,7 +317,7 @@ class ConstantPropagation extends Transform {
val stmtx = s map constPropStmt map constPropExpression
stmtx match {
case x: DefNode if !dontTouches.contains(x.name) => propagateRef(x.name, x.value)
- case Connect(_, WRef(wname, wtpe, WireKind, _), expr) if !dontTouches.contains(wname) =>
+ case Connect(_, WRef(wname, wtpe, WireKind, _), expr: Literal) if !dontTouches.contains(wname) =>
val exprx = constPropExpression(pad(expr, wtpe))
propagateRef(wname, exprx)
// Const prop registers that are fed only a constant or a mux between and constant and the
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index 380d53e5..e42ecfac 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -478,6 +478,36 @@ class ConstantPropagationSpec extends FirrtlFlatSpec {
"""
(parse(exec(input))) should be (parse(check))
}
+
+ "ConstProp" should "NOT swap wire names with node names" in {
+ val input =
+"""circuit Top :
+ module Top :
+ input clock : Clock
+ input x : UInt<1>
+ input y : UInt<1>
+ output z : UInt<1>
+ wire hit : UInt<1>
+ node _T_1 = or(x, y)
+ node _T_2 = eq(_T_1, UInt<1>(1))
+ hit <= _T_2
+ z <= hit
+"""
+ val check =
+"""circuit Top :
+ module Top :
+ input clock : Clock
+ input x : UInt<1>
+ input y : UInt<1>
+ output z : UInt<1>
+ wire hit : UInt<1>
+ node _T_1 = or(x, y)
+ node _T_2 = _T_1
+ hit <= _T_1
+ z <= hit
+"""
+ (parse(exec(input))) should be (parse(check))
+ }
}
// More sophisticated tests of the full compiler