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authorColin Schmidt2017-06-06 14:36:09 -0700
committerGitHub2017-06-06 14:36:09 -0700
commitfde7a6a7c8f08984095827cdbe0e3e4df5f1fab8 (patch)
tree10acfb0e472eb56b0b018ad96e86cbd7a9b78efd /src
parent562806aa9e95c4095fcb38c5a34421b6ddc6d3fe (diff)
Display the total time firrtl took to compile (#599)
* Display the total time firrtl took to compile * Switch timing print out to error(aka default)
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/Compiler.scala7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index a56fb793..5ef291da 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -416,7 +416,12 @@ trait Compiler extends LazyLogging {
def compile(state: CircuitState, customTransforms: Seq[Transform]): CircuitState = {
val allTransforms = CompilerUtils.mergeTransforms(transforms, customTransforms) :+ emitter
- val finalState = allTransforms.foldLeft(state) { (in, xform) => xform.runTransform(in) }
+ val (timeMillis, finalState) = Utils.time {
+ allTransforms.foldLeft(state) { (in, xform) => xform.runTransform(in) }
+ }
+
+ logger.error(f"Total FIRRTL Compile Time: $timeMillis%.1f ms")
+
finalState
}