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authorEdward Wang2017-09-01 15:24:51 -0700
committeredwardcwang2017-09-05 10:50:18 -0700
commitfce8867f9a9242f2f783867ced702d9d143dc60d (patch)
treef35e95576e23181b8a0f750c903146a9d1939ae9 /src
parentecaaa26e837b0d5d9a2085710ffa8d27dd07bd14 (diff)
Add InstanceGraph tests
Diffstat (limited to 'src')
-rw-r--r--src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala68
1 files changed, 68 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala b/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala
new file mode 100644
index 00000000..300fa8c4
--- /dev/null
+++ b/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala
@@ -0,0 +1,68 @@
+package firrtlTests.analyses
+
+import java.io._
+import org.scalatest._
+import org.scalatest.prop._
+import org.scalatest.Matchers._
+import firrtl.analyses.InstanceGraph
+import firrtl.graph.DiGraph
+import firrtl.Parser.parse
+import firrtl.passes._
+import firrtlTests._
+
+class InstanceGraphTests extends FirrtlFlatSpec {
+ private def getEdgeSet(graph: DiGraph[String]): Map[String, Set[String]] = {
+ (graph.getVertices map {v => (v, graph.getEdges(v))}).toMap
+ }
+
+ it should "recognize a simple hierarchy" in {
+ val input = """
+circuit Top :
+ module Top :
+ inst c1 of Child1
+ inst c2 of Child2
+ module Child1 :
+ inst a of Child1a
+ inst b of Child1b
+ skip
+ module Child1a :
+ skip
+ module Child1b :
+ skip
+ module Child2 :
+ skip
+"""
+ val circuit = ToWorkingIR.run(parse(input))
+ val graph = new InstanceGraph(circuit).graph.transformNodes(_.module)
+ getEdgeSet(graph) shouldBe Map("Top" -> Set("Child1", "Child2"), "Child1" -> Set("Child1a", "Child1b"), "Child2" -> Set(), "Child1a" -> Set(), "Child1b" -> Set())
+ }
+
+ it should "recognize disconnected hierarchies" in {
+ val input = """
+circuit Top :
+ module Top :
+ inst c of Child1
+ module Child1 :
+ skip
+
+ module Top2 :
+ inst a of Child2
+ inst b of Child3
+ skip
+ module Child2 :
+ inst a of Child2a
+ inst b of Child2b
+ skip
+ module Child2a :
+ skip
+ module Child2b :
+ skip
+ module Child3 :
+ skip
+
+"""
+ val circuit = ToWorkingIR.run(parse(input))
+ val graph = new InstanceGraph(circuit).graph.transformNodes(_.module)
+ getEdgeSet(graph) shouldBe Map("Top" -> Set("Child1"), "Top2" -> Set("Child2", "Child3"), "Child2" -> Set("Child2a", "Child2b"), "Child1" -> Set(), "Child2a" -> Set(), "Child2b" -> Set(), "Child3" -> Set())
+ }
+}