Replace IsInvalids on LowForm with connection to zero

1 files changed, 18 insertions, 5 deletions

diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala
index 9405c0f5..35323cbc 100644
--- a/src/main/scala/firrtl/passes/RemoveValidIf.scala
+++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala
@@ -5,17 +5,30 @@ package passes
 import firrtl.Mappers._
 import firrtl.ir._
 
-// Removes ValidIf as an optimization
+/** Remove ValidIf and replace IsInvalid with a connection to zero */
 object RemoveValidIf extends Pass {
-  // Recursive. Removes ValidIf's
+  // Recursive. Removes ValidIfs
   private def onExp(e: Expression): Expression = {
     e map onExp match {
-      case ValidIf(cond, value, tpe) => value
+      case ValidIf(_, value, _) => value
       case x => x
     }
   }
-  // Recursive.
-  private def onStmt(s: Statement): Statement = s map onStmt map onExp
+  private val UIntZero = Utils.zero
+  private val SIntZero = SIntLiteral(BigInt(0), IntWidth(1))
+  private val ClockZero = DoPrim(PrimOps.AsClock, Seq(UIntZero), Seq.empty, UIntZero.tpe)
+
+  // Recursive. Replaces IsInvalid with connecting zero
+  private def onStmt(s: Statement): Statement = s map onStmt map onExp match {
+    case invalid @ IsInvalid(info, loc) => loc.tpe match {
+      case _: UIntType => Connect(info, loc, UIntZero)
+      case _: SIntType => Connect(info, loc, SIntZero)
+      case _: AnalogType => invalid // Unclear what we should do, can't remove or we emit invalid Firrtl
+      case ClockType => Connect(info, loc, ClockZero)
+      case other => throw new Exception("Unexpected type ${other.serialize} on LowFirrtl")
+    }
+    case other => other
+  }
 
   private def onModule(m: DefModule): DefModule = {
     m match {