diff options
| author | Jack Koenig | 2017-05-17 20:13:26 -0700 |
|---|---|---|
| committer | GitHub | 2017-05-17 20:13:26 -0700 |
| commit | d824c60c9643973e0ae9cddc5007b3d9592f8a52 (patch) | |
| tree | 8c4d55c57d0eaf93411a9425f8795e66aba785c0 /src | |
| parent | 23f1b8d1f9f94975fb5b4fe22f15343d853808d9 (diff) | |
Make sure not to DCE input-only extmodules unless specified (#590)
Fixes #589
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/transforms/DeadCodeElimination.scala | 5 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/DCETests.scala | 23 |
2 files changed, 27 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala index 5199276c..bf7ff7eb 100644 --- a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala +++ b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala @@ -151,6 +151,9 @@ class DeadCodeElimination extends Transform { case ext: ExtModule => // Connect all inputs to all outputs val node = LogicNode(ext) + // Don't touch external modules *unless* they are specifically marked as doTouch + // Simply marking the extmodule itself is sufficient to prevent inputs from being removed + if (!doTouchExtMods.contains(ext.name)) depGraph.addEdge(circuitSink, node) ext.ports.foreach { case Port(_, pname, _, AnalogType(_)) => depGraph.addEdge(LogicNode(ext.name, pname), node) @@ -158,7 +161,7 @@ class DeadCodeElimination extends Transform { case Port(_, pname, Output, _) => val portNode = LogicNode(ext.name, pname) depGraph.addEdge(portNode, node) - // Don't touch external modules *unless* they are specifically marked as doTouch + // Also mark all outputs as circuit sinks (unless marked doTouch obviously) if (!doTouchExtMods.contains(ext.name)) depGraph.addEdge(circuitSink, portNode) case Port(_, pname, Input, _) => depGraph.addEdge(node, LogicNode(ext.name, pname)) } diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala index deb73b3b..129460e1 100644 --- a/src/test/scala/firrtlTests/DCETests.scala +++ b/src/test/scala/firrtlTests/DCETests.scala @@ -254,6 +254,29 @@ class DCETests extends FirrtlFlatSpec { | z <= x""".stripMargin exec(input, check) } + "Extmodule with only inputs" should "NOT be deleted by default" in { + val input = + """circuit Top : + | extmodule InputsOnly : + | input x : UInt<1> + | module Top : + | input x : UInt<1> + | output z : UInt<1> + | inst ext of InputsOnly + | ext.x <= x + | z <= x""".stripMargin + val check = + """circuit Top : + | extmodule InputsOnly : + | input x : UInt<1> + | module Top : + | input x : UInt<1> + | output z : UInt<1> + | inst ext of InputsOnly + | ext.x <= x + | z <= x""".stripMargin + exec(input, check) + } "Globally dead extmodule marked optimizable" should "be deleted" in { val input = """circuit Top : |