Prep for Scala 2.12 (#557)

* Update dependencies and JavaConverters for Scala 2.12

* Bump Scala (and library) version(s).

* replace "error" with "Utils.error"; bump Scala version to 2.11.11

9 files changed, 61 insertions, 56 deletions

diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 6c3911d6..a56fb793 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -7,10 +7,9 @@ import java.io.Writer
 import annotations._
 import scala.collection.mutable
 
+import firrtl.annotations._  // Note that wildcard imports are not great....
 import firrtl.ir.Circuit
-import passes.Pass
-import Utils.throwInternalError
-
+import firrtl.Utils.{error, throwInternalError}
 /**
  * RenameMap maps old names to modified names.  Generated by transformations
  * that modify names
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 32869dd3..69d27d23 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -14,7 +14,7 @@ import logger.LazyLogging
 
 object seqCat {
   def apply(args: Seq[Expression]): Expression = args.length match {
-    case 0 => error("Empty Seq passed to seqcat")
+    case 0 => Utils.error("Empty Seq passed to seqcat")
     case 1 => args.head
     case 2 => DoPrim(PrimOps.Cat, args, Nil, UIntType(UnknownWidth))
     case _ =>
@@ -29,7 +29,7 @@ object seqCat {
 object toBits {
   def apply(e: Expression): Expression = e match {
     case ex @ (_: WRef | _: WSubField | _: WSubIndex) => hiercat(ex)
-    case t => error("Invalid operand expression for toBits!")
+    case t => Utils.error("Invalid operand expression for toBits!")
   }
   private def hiercat(e: Expression): Expression = e.tpe match {
     case t: VectorType => seqCat((0 until t.size).reverse map (i =>
@@ -37,14 +37,14 @@ object toBits {
     case t: BundleType => seqCat(t.fields map (f =>
       hiercat(WSubField(e, f.name, f.tpe, UNKNOWNGENDER))))
     case t: GroundType => DoPrim(AsUInt, Seq(e), Seq.empty, UnknownType)
-    case t => error("Unknown type encountered in toBits!")
+    case t => Utils.error("Unknown type encountered in toBits!")
   }
 }
 
 object getWidth {
   def apply(t: Type): Width = t match {
     case t: GroundType => t.width
-    case _ => error("No width!")
+    case _ => Utils.error("No width!")
   }
   def apply(e: Expression): Width = apply(e.tpe)
 }
@@ -55,7 +55,7 @@ object bitWidth {
     case t: VectorType => t.size * bitWidth(t.tpe)
     case t: BundleType => t.fields.map(f => bitWidth(f.tpe)).foldLeft(BigInt(0))(_+_)
     case GroundType(IntWidth(width)) => width
-    case t => error("Unknown type encountered in bitWidth!")
+    case t => Utils.error("Unknown type encountered in bitWidth!")
   }
 }
 
@@ -72,7 +72,7 @@ object castRhs {
         DoPrim(AsClock, Seq(rhs), Seq.empty, lhst)
       case (_: UIntType, _) => 
         DoPrim(AsUInt, Seq(rhs), Seq.empty, lhst)
-      case (_, _) => error("castRhs lhst, rhs type combination is invalid")
+      case (_, _) => Utils.error("castRhs lhst, rhs type combination is invalid")
     }  
   }
 }
@@ -81,7 +81,7 @@ object fromBits {
   def apply(lhs: Expression, rhs: Expression): Statement = {
     val fbits = lhs match {
       case ex @ (_: WRef | _: WSubField | _: WSubIndex) => getPart(ex, ex.tpe, rhs, 0)
-      case _ => error("Invalid LHS expression for fromBits!")
+      case _ => Utils.error("Invalid LHS expression for fromBits!")
     }
     Block(fbits._2)
   }
@@ -112,7 +112,7 @@ object fromBits {
           (tmpOffset, stmts ++ substmts)
       }
       case t: GroundType => getPartGround(lhs, t, rhs, offset)
-      case t => error("Unknown type encountered in fromBits!")
+      case t => Utils.error("Unknown type encountered in fromBits!")
     }
 }
 
@@ -400,7 +400,7 @@ object Utils extends LazyLogging {
             ilen + get_size(t1x.tpe), jlen + get_size(t2x.tpe))
         }._1
       case (ClockType, ClockType) => if (flip1 == flip2) Seq((0, 0)) else Nil
-      case _ => error("shouldn't be here")
+      case _ => Utils.error("shouldn't be here")
     }
   }
 
@@ -446,9 +446,9 @@ object Utils extends LazyLogging {
   def get_field(v: Type, s: String): Field = v match {
     case vx: BundleType => vx.fields find (_.name == s) match {
       case Some(ft) => ft
-      case None => error("Shouldn't be here")
+      case None => Utils.error("Shouldn't be here")
     }
-    case vx => error("Shouldn't be here")
+    case vx => Utils.error("Shouldn't be here")
   }
 
   def times(flip: Orientation, d: Direction): Direction = times(flip, d)
@@ -587,7 +587,7 @@ object Utils extends LazyLogging {
             }
         }
         rootDecl
-      case e => error(s"getDeclaration does not support Expressions of type ${e.getClass}")
+      case e => Utils.error(s"getDeclaration does not support Expressions of type ${e.getClass}")
     }
   }
 
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index 222c2792..29b8a57b 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -4,7 +4,7 @@ package firrtl
 
 import org.antlr.v4.runtime.ParserRuleContext
 import org.antlr.v4.runtime.tree.TerminalNode
-import scala.collection.JavaConversions._
+import scala.collection.JavaConverters._
 import scala.collection.mutable
 import firrtl.antlr._
 import PrimOps._
@@ -64,19 +64,19 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
   }
 
   private def visitCircuit[FirrtlNode](ctx: FIRRTLParser.CircuitContext): Circuit =
-    Circuit(visitInfo(Option(ctx.info), ctx), ctx.module.map(visitModule), ctx.id.getText)
+    Circuit(visitInfo(Option(ctx.info), ctx), ctx.module.asScala.map(visitModule), ctx.id.getText)
 
   private def visitModule[FirrtlNode](ctx: FIRRTLParser.ModuleContext): DefModule = {
     val info = visitInfo(Option(ctx.info), ctx)
     ctx.getChild(0).getText match {
-      case "module" => Module(info, ctx.id.getText, ctx.port.map(visitPort),
+      case "module" => Module(info, ctx.id.getText, ctx.port.asScala.map(visitPort),
         if (ctx.moduleBlock() != null)
           visitBlock(ctx.moduleBlock())
         else EmptyStmt)
       case "extmodule" =>
         val defname = if (ctx.defname != null) ctx.defname.id.getText else ctx.id.getText
-        val ports = ctx.port map visitPort
-        val params = ctx.parameter map visitParameter
+        val ports = ctx.port.asScala map visitPort
+        val params = ctx.parameter.asScala map visitParameter
         ExtModule(info, ctx.id.getText, ports, defname, params)
     }
   }
@@ -131,7 +131,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
           case "Clock" => ClockType
           case "Analog" => if (ctx.getChildCount > 1) AnalogType(IntWidth(string2BigInt(ctx.intLit(0).getText)))
           else AnalogType(UnknownWidth)
-          case "{" => BundleType(ctx.field.map(visitField))
+          case "{" => BundleType(ctx.field.asScala.map(visitField))
         }
       case typeContext: TypeContext => new VectorType(visitType(ctx.`type`), string2Int(ctx.intLit(0).getText))
     }
@@ -143,10 +143,10 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
   }
 
   private def visitBlock[FirrtlNode](ctx: FIRRTLParser.ModuleBlockContext): Statement =
-    Block(ctx.simple_stmt().map(_.stmt).filter(_ != null).map(visitStmt))
+    Block(ctx.simple_stmt().asScala.map(_.stmt).filter(_ != null).map(visitStmt))
 
   private def visitSuite[FirrtlNode](ctx: FIRRTLParser.SuiteContext): Statement =
-    Block(ctx.simple_stmt().map(_.stmt).filter(_ != null).map(visitStmt))
+    Block(ctx.simple_stmt().asScala.map(_.stmt).filter(_ != null).map(visitStmt))
 
 
   // Memories are fairly complicated to translate thus have a dedicated method
@@ -159,12 +159,12 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
 
     def parseMemFields(memFields: Seq[MemFieldContext]): Unit =
       memFields.foreach { field =>
-        val fieldName = field.children(0).getText
+        val fieldName = field.children.asScala(0).getText
 
         fieldName match {
-          case "reader" => readers ++= field.id().map(_.getText)
-          case "writer" => writers ++= field.id().map(_.getText)
-          case "readwriter" => readwriters ++= field.id().map(_.getText)
+          case "reader" => readers ++= field.id().asScala.map(_.getText)
+          case "writer" => writers ++= field.id().asScala.map(_.getText)
+          case "readwriter" => readwriters ++= field.id().asScala.map(_.getText)
           case _ =>
             val paramDef = fieldName match {
               case "data-type" => ParamValue(typ = Some(visitType(field.`type`())))
@@ -174,7 +174,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
             if (fieldMap.contains(fieldName))
               throw new ParameterRedefinedException(s"Redefinition of $fieldName in FIRRTL line:${field.start.getLine}")
             else
-              fieldMap += fieldName -> paramDef
+              fieldMap(fieldName) = paramDef
         }
       }
 
@@ -182,7 +182,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
 
     // Build map of different Memory fields to their values
     try {
-      parseMemFields(ctx.memField())
+      parseMemFields(ctx.memField().asScala)
     } catch {
       // attach line number
       case e: ParameterRedefinedException => throw new ParameterRedefinedException(s"[$info] ${e.message}")
@@ -217,7 +217,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
     val alt: Statement =
       if (ctx.when() != null)
         visitWhen(ctx.when())
-      else if (ctx.suite().length > 1)
+      else if (ctx.suite().asScala.length > 1)
         visitSuite(ctx.suite(1))
       else
         EmptyStmt
@@ -227,6 +227,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
 
   // visitStmt
   private def visitStmt[FirrtlNode](ctx: FIRRTLParser.StmtContext): Statement = {
+    val ctx_exp = ctx.exp.asScala
     val info = visitInfo(Option(ctx.info), ctx)
     ctx.getChild(0) match {
       case when: WhenContext => visitWhen(when)
@@ -244,7 +245,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
             else
               (UIntLiteral(0, IntWidth(1)), Reference(name, tpe))
           }
-          DefRegister(info, name, tpe, visitExp(ctx.exp(0)), reset, init)
+          DefRegister(info, name, tpe, visitExp(ctx_exp(0)), reset, init)
         case "mem" => visitMem(ctx)
         case "cmem" =>
           val t = visitType(ctx.`type`())
@@ -263,21 +264,21 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
             }: Must provide cmem with vector type")
           }
         case "inst" => DefInstance(info, ctx.id(0).getText, ctx.id(1).getText)
-        case "node" => DefNode(info, ctx.id(0).getText, visitExp(ctx.exp(0)))
+        case "node" => DefNode(info, ctx.id(0).getText, visitExp(ctx_exp(0)))
 
-        case "stop(" => Stop(info, string2Int(ctx.intLit().getText), visitExp(ctx.exp(0)), visitExp(ctx.exp(1)))
-        case "attach" => Attach(info, ctx.exp map visitExp)
-        case "printf(" => Print(info, visitStringLit(ctx.StringLit), ctx.exp.drop(2).map(visitExp),
-          visitExp(ctx.exp(0)), visitExp(ctx.exp(1)))
+        case "stop(" => Stop(info, string2Int(ctx.intLit().getText), visitExp(ctx_exp(0)), visitExp(ctx_exp(1)))
+        case "attach" => Attach(info, ctx_exp map visitExp)
+        case "printf(" => Print(info, visitStringLit(ctx.StringLit), ctx_exp.drop(2).map(visitExp),
+          visitExp(ctx_exp(0)), visitExp(ctx_exp(1)))
         case "skip" => EmptyStmt
       }
       // If we don't match on the first child, try the next one
       case _ =>
         ctx.getChild(1).getText match {
-          case "<=" => Connect(info, visitExp(ctx.exp(0)), visitExp(ctx.exp(1)))
-          case "<-" => PartialConnect(info, visitExp(ctx.exp(0)), visitExp(ctx.exp(1)))
-          case "is" => IsInvalid(info, visitExp(ctx.exp(0)))
-          case "mport" => CDefMPort(info, ctx.id(0).getText, UnknownType, ctx.id(1).getText, Seq(visitExp(ctx.exp(0)), visitExp(ctx.exp(1))), visitMdir(ctx.mdir))
+          case "<=" => Connect(info, visitExp(ctx_exp(0)), visitExp(ctx_exp(1)))
+          case "<-" => PartialConnect(info, visitExp(ctx_exp(0)), visitExp(ctx_exp(1)))
+          case "is" => IsInvalid(info, visitExp(ctx_exp(0)))
+          case "mport" => CDefMPort(info, ctx.id(0).getText, UnknownType, ctx.id(1).getText, Seq(visitExp(ctx_exp(0)), visitExp(ctx_exp(1))), visitMdir(ctx.mdir))
         }
     }
   }
@@ -285,7 +286,8 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
   // TODO
   // - Add mux
   // - Add validif
-  private def visitExp[FirrtlNode](ctx: FIRRTLParser.ExpContext): Expression =
+  private def visitExp[FirrtlNode](ctx: FIRRTLParser.ExpContext): Expression = {
+    val ctx_exp = ctx.exp.asScala
     if (ctx.getChildCount == 1)
       Reference(ctx.getText, UnknownType)
     else
@@ -317,12 +319,12 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
               (IntWidth(BigInt(width)), value)
             }
           SIntLiteral(value, width)
-        case "validif(" => ValidIf(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), UnknownType)
-        case "mux(" => Mux(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), visitExp(ctx.exp(2)), UnknownType)
+        case "validif(" => ValidIf(visitExp(ctx_exp(0)), visitExp(ctx_exp(1)), UnknownType)
+        case "mux(" => Mux(visitExp(ctx_exp(0)), visitExp(ctx_exp(1)), visitExp(ctx_exp(2)), UnknownType)
         case _ =>
           ctx.getChild(1).getText match {
             case "." =>
-              val expr1 = visitExp(ctx.exp(0))
+              val expr1 = visitExp(ctx_exp(0))
               // TODO Workaround for #470
               if (ctx.fieldId == null) {
                 ctx.DoubleLit.getText.split('.') match {
@@ -335,13 +337,14 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode] {
                 new SubField(expr1, ctx.fieldId.getText, UnknownType)
               }
             case "[" => if (ctx.exp(1) == null)
-              new SubIndex(visitExp(ctx.exp(0)), string2Int(ctx.intLit(0).getText), UnknownType)
-            else new SubAccess(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), UnknownType)
+              new SubIndex(visitExp(ctx_exp(0)), string2Int(ctx.intLit(0).getText), UnknownType)
+            else new SubAccess(visitExp(ctx_exp(0)), visitExp(ctx_exp(1)), UnknownType)
             // Assume primop
-            case _ => DoPrim(visitPrimop(ctx.primop), ctx.exp.map(visitExp),
-              ctx.intLit.map(x => string2BigInt(x.getText)), UnknownType)
+            case _ => DoPrim(visitPrimop(ctx.primop), ctx_exp.map(visitExp),
+              ctx.intLit.asScala.map(x => string2BigInt(x.getText)), UnknownType)
           }
       }
+  }
 
   // stripSuffix("(") is included because in ANTLR concrete syntax we have to include open parentheses,
   //  see grammar file for more details
diff --git a/src/main/scala/firrtl/annotations/AnnotationUtils.scala b/src/main/scala/firrtl/annotations/AnnotationUtils.scala
index 8f55c13e..1cdb7d18 100644
--- a/src/main/scala/firrtl/annotations/AnnotationUtils.scala
+++ b/src/main/scala/firrtl/annotations/AnnotationUtils.scala
@@ -7,6 +7,7 @@ import net.jcazevedo.moultingyaml._
 import firrtl.annotations.AnnotationYamlProtocol._
 
 import firrtl.ir._
+import firrtl.Utils.error
 
 object AnnotationUtils {
   def toYaml(a: Annotation): String = a.toYaml.prettyPrint
diff --git a/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala b/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala
index 2e151741..05604bd8 100644
--- a/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala
+++ b/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala
@@ -7,7 +7,7 @@ import firrtl.PrimOps._
 import firrtl.ir._
 import firrtl._
 import firrtl.Mappers._
-import firrtl.Utils.{sub_type, module_type, field_type, BoolType, max, min, pow_minus_one}
+import firrtl.Utils.{sub_type, module_type, field_type, max, error}
 
 /** Replaces FixedType with SIntType, and correctly aligns all binary points
   */
diff --git a/src/main/scala/firrtl/passes/memlib/YamlUtils.scala b/src/main/scala/firrtl/passes/memlib/YamlUtils.scala
index 75a62245..4cc28e42 100644
--- a/src/main/scala/firrtl/passes/memlib/YamlUtils.scala
+++ b/src/main/scala/firrtl/passes/memlib/YamlUtils.scala
@@ -3,7 +3,9 @@
 package firrtl.passes
 package memlib
 import net.jcazevedo.moultingyaml._
-import java.io.{File, CharArrayWriter, PrintWriter}
+import java.io.{CharArrayWriter, File, PrintWriter}
+
+import firrtl.Utils.error
 
 object CustomYAMLProtocol extends DefaultYamlProtocol {
   // bottom depends on top
diff --git a/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala b/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala
index 3f1dfa46..ccd6d9c0 100644
--- a/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala
+++ b/src/main/scala/tutorial/lesson1-circuit-traversal/AnalyzeCircuit.scala
@@ -4,7 +4,7 @@ package tutorial
 package lesson1
 
 // Compiler Infrastructure
-import firrtl.{Transform, LowForm, CircuitState}
+import firrtl.{Transform, LowForm, CircuitState, Utils}
 // Firrtl IR classes
 import firrtl.ir.{Circuit, DefModule, Statement, Expression, Mux}
 // Map functions
@@ -31,7 +31,7 @@ class Ledger {
     case Some(name) => moduleMuxMap(name) = moduleMuxMap.getOrElse(name, 0) + 1
   }
   def getModuleName: String = moduleName match {
-    case None => error("Module name not defined in Ledger!")
+    case None => Utils.error("Module name not defined in Ledger!")
     case Some(name) => name
   }
   def setModuleName(myName: String): Unit = {
diff --git a/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala b/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala
index bdf6f665..6236703f 100644
--- a/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala
+++ b/src/main/scala/tutorial/lesson2-working-ir/AnalyzeCircuit.scala
@@ -4,7 +4,7 @@ package tutorial
 package lesson2
 
 // Compiler Infrastructure
-import firrtl.{Transform, LowForm, CircuitState}
+import firrtl.{Transform, LowForm, CircuitState, Utils}
 // Firrtl IR classes
 import firrtl.ir.{Circuit, DefModule, Statement, DefInstance, Expression, Mux}
 // Firrtl compiler's working IR classes (WIR)
@@ -133,7 +133,7 @@ class AnalyzeCircuit extends Transform {
       // IR node [[DefInstance]] is previously replaced by WDefInstance, a
       //  "working" IR node
       case DefInstance(info, name, module) => 
-        error("All DefInstances should have been replaced by WDefInstances")
+        Utils.error("All DefInstances should have been replaced by WDefInstances")
       // Working IR Node [[WDefInstance]] is what the compiler uses
       // See src/main/scala/firrtl/WIR.scala for all working IR nodes
       case WDefInstance(info, name, module, tpe) =>
diff --git a/src/test/scala/firrtlTests/ParserSpec.scala b/src/test/scala/firrtlTests/ParserSpec.scala
index b030be8e..66e214a1 100644
--- a/src/test/scala/firrtlTests/ParserSpec.scala
+++ b/src/test/scala/firrtlTests/ParserSpec.scala
@@ -57,8 +57,8 @@ class ParserSpec extends FirrtlFlatSpec {
       firrtl.Parser.parse((prelude ++ fieldsToSeq(fields) :+ s"      ${k} => ${v}"))
 
     Seq("data-type", "depth", "read-latency", "write-latency") foreach { field =>
-      evaluating { parseWithoutField(field) } should produce [ParameterNotSpecifiedException]
-      evaluating { parseWithDuplicate(field, fields(field)) } should produce [ParameterRedefinedException]
+      an [ParameterNotSpecifiedException] should be thrownBy { parseWithoutField(field) }
+      an [ParameterRedefinedException] should be thrownBy { parseWithDuplicate(field, fields(field)) }
     }
   }