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AgeCommit message (Expand)Author
2016-02-24Make rocket.fir regression test fail nicer on consolejackkoenig
2016-02-24Quick fix for printf in the emitted VerilogKamyar Mohajerani
2016-02-23Add rocket regression, just runs rocket.fir through Verilog compiler and comp...Jack
2016-02-23Change FIRRTL Compiler to remove CHIRRTL and Check High FIRRTL FormJack
2016-02-23Stop closing writers in compiler, close in Driver instead (allows others to u...Jack
2016-02-22Change default log-level to warn, users should change manually if so desiredJack
2016-02-22Temporary Fix: get_type on depth=1 memories causing IntWidth(0) typesJack
2016-02-10Re-enable some passesPalmer Dabbelt
2016-02-09Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2016-02-09Added license to FIRRTL filesazidar
2016-02-09Added remaining check passes. Ready for open sourcingazidar
2016-02-09CHIRRTL passes work, parser is updatedazidar
2016-02-09Bug Fixes in handling hyphens as part of IDs, proper handling of negative Int...Jack
2016-02-09Added migrated HighFormCheck to Scala FIRRTL, changes to IR and Utils for get...Jack
2016-02-09Added chirrtl passes, need to update parserazidar
2016-02-09More bug fixesazidar
2016-02-09Added constprop,v-wrap,v-rename. All set to attempt like->like comparison of ...azidar
2016-02-09Added Lower Types.azidar
2016-02-09Fixed Visitor incorrectly handling Vectors of UnknownWidth UInts and SIntsJack
2016-02-09Added Expand Whens passazidar
2016-02-09Adding ScalaTest for unit testing of Scala FIRRTL. Added a few basic tests fo...Jack
2016-02-09Fix bug in mem serializationJack
2016-02-09Fix start counting from 1 instead of 0 bugJack
2016-02-09Updated SInt/UInt emission to match stanza. Still need to update to new syntax.azidar
2016-02-09Fixed port emissionazidar
2016-02-09Moved passes to new packageazidar
2016-02-09Moved check-high-form to operate on working irazidar
2016-02-09Changed stanza output of UInt/SInt to include widths. Made tests match accord...azidar
2016-02-09Added remove accessesazidar
2016-02-09Restructure passes to be new subpackage with more modular design, add new str...Jack
2016-02-09Fix serialize bugs: WSub(Field|Index|Access) printing extraneous w, module no...Jack
2016-02-09Added expand connect. Resolve now includes to working irazidar
2016-02-09Added resolve gendersazidar
2016-02-09WIP. Finished to working ir, resolve kinds, and infer typesazidar
2016-02-09WIP. Got to-working-ir workingazidar
2016-02-09WIP, nothing works. Starting creating working IR and necessary utilsazidar
2016-02-08Escape quotes in strings before emitting as VerilogPalmer Dabbelt
2016-02-08Escape printf argument before emitting themPalmer Dabbelt
2016-01-29Fix no space after "flip" for flipped fields in Scala FIRRTL, also make Scala...Jack
2016-01-29Changed reg syntax to new "with" semantics in Scala FIRRTLJack
2016-01-28Add support for single-line and multi-line scoping to Scala FIRRTL preprocess...Jack
2016-01-28Fixed bug on translating SubAccess concrete syntax to abstract in Scala FIRRTLJack
2016-01-28WIP Added support for mux to Scala FIRRTLjackkoenig
2016-01-28WIP Added support for is invalid and validif to Scala FIRRTLjackkoenig
2016-01-28WIP Added support for stop to Scala FIRRTLjackkoenig
2016-01-28WIP Added support for printf to Scala FIRRTLjackkoenig
2016-01-28WIP: Added support for FIRRTL 0.2.0 Memories to Scala FIRRTLjackkoenig
2016-01-28Move IntLit ANTLR lexer rule to before String lexer rule to ensure IntLit of ...jackkoenig
2016-01-28Merge branch 'new-reg-prims' of github.com:ucb-bar/firrtlazidar
2016-01-28Fixed bug where subaccess indexes were being classified as female,azidar
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