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authorazidar2016-02-09 18:58:54 -0800
committerazidar2016-02-09 18:58:54 -0800
commit55ab528a3e8efaecf62163828f30cbd249623028 (patch)
treefbece16ec93f233f03945ecf187e2f2a69d5cb44 /src
parent4160ffa5c86ff7f4d5534dec3624b7127263b782 (diff)
parentf0533bd701d372344af7e5827071148e9b37322c (diff)
Merge branch 'master' of github.com:ucb-bar/firrtl
Diffstat (limited to 'src')
-rw-r--r--src/main/stanza/passes.stanza4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index d0182532..cb4607b8 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2438,6 +2438,8 @@ defn escape (s:String) -> String :
for c in s do :
if c == '\n' :
add(s*,"\\n")
+ else if c == '"' :
+ add(s*, "\\\"")
else :
if c == 'x' and percent :
add(s*,"h")
@@ -2694,7 +2696,7 @@ defn emit-verilog (m:InModule) -> Module :
defn stop (ret:Int) -> Streamable :
["$fdisplay(32'h80000002,\"" ret "\");$finish;"]
defn printf (str:String,args:List<Expression>) -> Streamable :
- val str* = join(List(escape(str),args),",")
+ val str* = join(List(escape(str),map(escape,map(to-string,args))),",")
["$fwrite(32'h80000002," str* ");"]
defn delay (e:Expression, n:Int, clk:Expression) -> Expression :
var e* = e