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2016-01-24Added muxing on passive aggregate typesazidar
2016-01-24Merge branch 'new-mem' of github.com:ucb-bar/firrtl into new-memazidar
2016-01-24Removed hashing as it made refchip slower to compileazidar
2016-01-24Added DefMemory to CInfer Typesazidar
2016-01-23Fix Verilog syntax errors for print/stopAndrew Waterman
2016-01-23Removed buggy optimization of dshr and dshlazidar
2016-01-23Moved inst declarations after other declarationsazidar
2016-01-23Fixed commas for instances in verilogazidar
2016-01-23Added more semicolonsazidar
2016-01-23Added semicolon after assigns in verilogazidar
2016-01-23off by one error when emitting ports in verilogazidar
2016-01-23Fixed combinational read verilog backendazidar
2016-01-23Removed more prints ;)azidar
2016-01-23Removed print statementsazidar
2016-01-23Fixed bug where the write mask wasn't being generated correctlyazidar
2016-01-23Removed debugging printlnsazidar
2016-01-23Added inference to mportsazidar
2016-01-23Added prefix checker, now compliant with firrtl specazidar
2016-01-23Changed chirrtl to not require known mask valuesazidar
2016-01-20WIP, need to update chirrtl with new mask syntaxazidar
2016-01-17Forgot to add the changesazidar
2016-01-17Removed temporary filesazidar
2016-01-17BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed testsazidar
2016-01-16Standard Verilog doesn't use Resolve(), but lists out the resolution passes i...azidar
2016-01-16Fixed bug in lowering memories that had aggregate data typesazidar
2016-01-16Fixed bug in check-init that allows it to check on non-lowered thingsazidar
2016-01-16Moved back to create-exps instead of fast-create-exps to fix bug - fast-creat...azidar
2016-01-16Nodes must now be ground typesazidar
2016-01-16Fixed up minor errors after rebase onto masterazidar
2016-01-16Reworked Verilog emission of registers to if/else instead of ?:azidar
2016-01-16No longer split on muxesazidar
2016-01-16Commented back in Starting and Finishing for testingazidar
2016-01-16Sped up remove access by checking a conditionazidar
2016-01-16Added more data in printout of time to compileazidar
2016-01-16printf no longer includes a new lineazidar
2016-01-16Verilog emission no longer casts input to shr or bit selectazidar
2016-01-16Added hashed on get flipazidar
2016-01-16Sped up some passes. Added global mname to allow easy per-module hashes for a...azidar
2016-01-16Made create-exps a bit fasterazidar
2016-01-16Finished first cut at new firrtl - time for testing! Chirrtl requires masks t...azidar
2016-01-16Fixed a bunch of tests, and minor bugsazidar
2016-01-16Added src and test filesazidar
2016-01-16WIP adding chirrtlazidar
2016-01-16WIP Almost there, need to generate enable connectionsazidar
2016-01-16WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl...azidar
2016-01-16WIP getting through testsazidar
2016-01-16Finished supporting nested accesses. Required some nuianced thinking. Pass al...azidar
2016-01-16WIP, hit semantic bug in WSubAccessazidar
2016-01-16New memory works with verilog. Slowly changing tests and fixing bugs.azidar
2016-01-16WIP. Compiles and almost done with verilog backend. Need to think about emitt...azidar
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