| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-01-08 | Typo: ExecutionOptionManager -> ExecutionOptionsManager. | Leway Colin | |
| 2017-12-29 | Add support for multiple annotation files | Jack | |
| Change loadAnnotations to return annotations instead of mutating firrtlOptions Deprecate implicit annotation file (top.anno) and annotation file override | |||
| 2017-12-29 | Remove option --force-append-anno-file, make default | Jack Koenig | |
| The logic around this option was unintuitive and led to silently dropped annotations. | |||
| 2017-12-27 | Removed top preamble (#640) | Adam Izraelevitz | |
| 2017-12-22 | API change: out-of-bounds vec accesses now invalid, not first element (#685) | Adam Izraelevitz | |
| [skip formal checks] Generate nicer name for remove accesses | |||
| 2017-12-20 | Verify shl/shr amount is > 0 (#710) | Jim Lawson | |
| Fixes #527 | |||
| 2017-12-20 | Fix bug in ConstProp where module dependency edges were dropped (#696) | Jack Koenig | |
| This resulted in parent modules sometimes being constant proppagated before a child module. If the child module has a constant driving one of its outputs, the parent module would thus not see the constant. This resulted in strange unstable constant propagation behavior where sometimes constant outputs would not propagate. Also add test illustrating why this occurs with uses of InstanceGraph | |||
| 2017-12-20 | Make submodule inputs void in ExpandWhens (#706) | Jack Koenig | |
| 2017-12-19 | Make toNamed invert serialize (#709) | Schuyler Eldridge | |
| Fixes #708 | |||
| 2017-12-12 | Add RemoveWires transform | Jack Koenig | |
| This transform replaces all wires with nodes in a legal, flow-forward order | |||
| 2017-11-28 | Have DedupModules report renaming | Jack | |
| 2017-11-28 | Refactor RenameMap to rename Components if their Module is renamed | Jack | |
| 2017-11-16 | Move digraph exceptions out of digraph class (#688) | Albert Magyar | |
| 2017-11-10 | Make digraph methods deterministic (#653) | Albert Magyar | |
| 2017-11-08 | Add InfoSpec for checking Info propagation | Jack Koenig | |
| 2017-11-08 | Add FirrtlCheckers and scalatest helpers for testing | Jack Koenig | |
| 2017-10-31 | Fix bug emitting and reparsing ExtModule String parameters (#675) | Jack Koenig | |
| 2017-09-30 | Make ReplaceAccesses optimize multi-dimensional accesses (#665) | Albert Magyar | |
| 2017-09-30 | Fixed zero width cat but (#651) | Adam Izraelevitz | |
| 2017-09-29 | StringLit.verilogEscape should support all printable ASCII chars (#668) | Jack Koenig | |
| Defined as the range from ' ' to '~' [0x20, 0x7e] | |||
| 2017-09-29 | Namespace - only save suffix for temp names (#667) | Jack Koenig | |
| This prevents collisions for one prefix (including temp) from incrementing the suffix for other prefixes. Makes names more stable. | |||
| 2017-09-22 | Fix string lit (#663) | Jack Koenig | |
| Refactor StringLit to use String instead of Array[Byte] | |||
| 2017-09-19 | Create way of collecting program arguments in Driver (#659) | Chick Markley | |
| Adds programArgs to commonOptions programArgs is all arguments on command line with out leading -/+ or are not bound to a flag. Create simple test | |||
| 2017-09-06 | Write tests on multi-rooted circuits for ConstProp | Edward Wang | |
| Since InstanceGraph now has all modules in its graph, test ConstProp on all modules as a default behaviour. - Need to think about how to target ConstProp only for a specific module? Close #644 | |||
| 2017-09-05 | Add InstanceGraph tests | Edward Wang | |
| 2017-08-23 | Reorder port and wire assignments in Verilog (#641) | Adam Izraelevitz | |
| * Reorder port and wire assignments in Verilog * Fixed up syntax | |||
| 2017-08-14 | Constant propagation across module boundaries (#633) | Jack Koenig | |
| 2017-08-04 | bug fix for cases when we want to flatten a module in which a module is ↵ | Andrey Ayupov | |
| instantiated multiple times (#634) | |||
| 2017-08-01 | DCE for IsInvalid (#629) | Donggyu | |
| 2017-07-26 | Flatten transformation (#631) | Andrey Ayupov | |
| * initial implementation of InlineDeepTransformation * rewrote transformation to not have any side effects in terms on inlining that was not annotated to be inlined * minor rewrites * renamed transformations to Flatten * fixes according to review * added more comments and fixed formating/style * fixed spacing, minor style fixes | |||
| 2017-07-17 | do not swap wire names with node names | Donggyu Kim | |
| 2017-07-17 | Fix ConstProp bug where multiple names would swap with one | Jack Koenig | |
| Fixes issue in https://github.com/freechipsproject/rocket-chip/pull/848 | |||
| 2017-07-14 | Fix bug in DiGraph.reverse on an graph with one vertex, no edges (#628) | Jack Koenig | |
| 2017-07-06 | Fixed inability to disable combo loop check (#619) | Chick Markley | |
| * Fixed inability to disable combo loop check Moved checking of dontCheckComboLoops into loadAnnotations so that it works in cases where Driver.execute is not used. * Fix test for annotations, modifications to loadAnnotations made 2 more annotations visible. * Remove debug println from DriverSpec | |||
| 2017-06-29 | ConstProp registers that are only connected to or reset to a consant | Jack Koenig | |
| 2017-06-29 | Add test for padding constant connections to wires in ConstProp | Jack Koenig | |
| 2017-06-29 | Preserve "better" names in Constant Propagation | Jack Koenig | |
| Names that do not start with '_' are "better" than those that do | |||
| 2017-06-28 | Make Constant Propagation respect dontTouch | Jack Koenig | |
| Constant Propagation will not optimize across components marked dontTouch | |||
| 2017-06-28 | Promote ConstProp to a transform | Jack Koenig | |
| 2017-06-28 | [Testing] Clean up SimpleTransformSpec execute methods | Jack Koenig | |
| This makes it more concise to write tests | |||
| 2017-06-28 | [Testing] Have SimpleTransformSpec mix in FirrtlMatchers | Jack Koenig | |
| Gives all transform specs access to useful utilities (like dontTouch). Deletes some duplicate code. Parsing mode UseInfo is fine for everything, only matters if the test actually uses info. | |||
| 2017-06-27 | Emitting reg update mux tree, only walk netlist for wires and nodes | Jack Koenig | |
| Fixes bug where the Verilog emitter could pull the next value for a register that feeds a second register, removing the first register from the second register's update. | |||
| 2017-06-26 | Add support for wires in ConstProp | Jack Koenig | |
| This requires a quick second pass to back propagate constant wires but the QoR win is substantial. We also only need to count back propagations in determining whether to run ConstProp again which shaves off an iteration in the common case. | |||
| 2017-06-21 | Add --no-dce command-line option to skip DCE | Jack Koenig | |
| 2017-06-13 | Make ExpandWhens delete 'is invalid' for attached Analog components | Jack Koenig | |
| Also add tests for what should happen to 'is invalid' in ExpandWhens Fixes #606 | |||
| 2017-06-13 | Style changes to ExpandWhensSpec | Jack Koenig | |
| 2017-06-12 | Add option to disable combinational loop detection | Jack Koenig | |
| Resolves #600 | |||
| 2017-06-12 | Move CheckCombLoops from passes/ to transforms/ | Jack Koenig | |
| 2017-06-12 | Fixes a typo in the verilog `elsif code generation (#603) | Shreesha Srinath | |
| 2017-05-27 | Prep for Scala 2.12 (#557) | Jim Lawson | |
| * Update dependencies and JavaConverters for Scala 2.12 * Bump Scala (and library) version(s). * replace "error" with "Utils.error"; bump Scala version to 2.11.11 | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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