Removed top preamble (#640)

2 files changed, 47 insertions, 34 deletions

diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala
index 6e5883d7..cf92ec1c 100644
--- a/src/test/scala/firrtlTests/AttachSpec.scala
+++ b/src/test/scala/firrtlTests/AttachSpec.scala
@@ -233,6 +233,36 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
        |endmodule""".stripMargin.split("\n") map normalized
     executeTest(input, check, compiler)
   }
+
+  it should "not error if not isinvalid" in {
+    val compiler = new VerilogCompiler
+    val input =
+     """circuit Attaching :
+        |  module Attaching :
+        |    output an: Analog<3>
+        |""".stripMargin
+    val check =
+     """module Attaching(
+       |  inout  [2:0] an
+       |);
+       |endmodule""".stripMargin.split("\n") map normalized
+    executeTest(input, check, compiler)
+  }
+  it should "not error if isinvalid" in {
+    val compiler = new VerilogCompiler
+    val input =
+     """circuit Attaching :
+        |  module Attaching :
+        |    output an: Analog<3>
+        |    an is invalid
+        |""".stripMargin
+    val check =
+     """module Attaching(
+       |  inout  [2:0] an
+       |);
+       |endmodule""".stripMargin.split("\n") map normalized
+    executeTest(input, check, compiler)
+  }
 }
 
 class AttachAnalogSpec extends FirrtlFlatSpec {
diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala
index 39d54755..348ed300 100644
--- a/src/test/scala/firrtlTests/CompilerTests.scala
+++ b/src/test/scala/firrtlTests/CompilerTests.scala
@@ -133,40 +133,23 @@ circuit Top :
  * to the correct Verilog.
  */
 class VerilogCompilerSpec extends CompilerSpec with Matchers {
-   val compiler = new VerilogCompiler()
-   val input =
-"""
-circuit Top :
-  module Top :
-    input a : UInt<1>[2]
-    output b : UInt<1>[2]
-    b <= a
-"""
-   val check = Seq(
-      "`ifdef RANDOMIZE_GARBAGE_ASSIGN",
-      "`define RANDOMIZE",
-      "`endif",
-      "`ifdef RANDOMIZE_INVALID_ASSIGN",
-      "`define RANDOMIZE",
-      "`endif",
-      "`ifdef RANDOMIZE_REG_INIT",
-      "`define RANDOMIZE",
-      "`endif",
-      "`ifdef RANDOMIZE_MEM_INIT",
-      "`define RANDOMIZE",
-      "`endif",
-      "",
-      "module Top(",
-      "  input   a_0,",
-      "  input   a_1,",
-      "  output  b_0,",
-      "  output  b_1",
-      ");",
-      "  assign b_0 = a_0;",
-      "  assign b_1 = a_1;",
-      "endmodule\n"
-   ).reduce(_ + "\n" + _)
-   "A circuit's verilog output" should "match the given string" in {
+   val input = """circuit Top :
+                 |  module Top :
+                 |    input a : UInt<1>[2]
+                 |    output b : UInt<1>[2]
+                 |    b <= a""".stripMargin
+   val check = """module Top(
+                 |  input   a_0,
+                 |  input   a_1,
+                 |  output  b_0,
+                 |  output  b_1
+                 |);
+                 |  assign b_0 = a_0;
+                 |  assign b_1 = a_1;
+                 |endmodule
+                 |""".stripMargin
+   def compiler = new VerilogCompiler()
+   "A circuit's verilog output" should "match the given string and not have RANDOMIZE if no invalids" in {
       getOutput should be (check)
    }
 }