| Age | Commit message (Collapse) | Author |
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Also delete CircuitTopName. It will not work with updated RenameMap
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Moved from RemoveValidIf
Also Make RemoveValidIf.getGroundZero public and support Fixed
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Improve constant propagation of connections to references
[skip formal checks]
LEC fails on this PR because this PR actually changes the circuit. The
change is that it constant propagates some additional registers. This is
really just extending #621 to work on more registers that it was
supposed to be propagating anyway.
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* Propagate exceptions from JsonProtocol deserialization
* Add AnnotationFileNotFoundException for better error reporting
* Add AnnotationClassNotFoundException for better error reporting
* Better propagate JSON parsing errors
Also report the file if there is a error deserializing a JSON file
* Make exception for non-array JSON file more explicit
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* Added grouping pass
* Added InfoMagnet and infomappers
* Changed return type of execute to allow final CircuitState inspection
* Updated dedup. Now is name-agnostic
* Added GroupAndDedup transform
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Also make ParserException extend FIRRTLException to better report parsing
errors to the user
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* Pass up annotations in return value from Driver.execute
Backward compatible with existing usage.
Adds CircuitState to FirrtlExecutionSuccess, but
that member is not part of the unapply.
"To a single file per module if OneFilePerModule is specified"
test shows example of getting access to annotations
* As experiment return created files in annotations
Fix line missed in last push
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Closes #666.
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Also make InvalidAnnotationFileException extend FIRRTLException for better
error reporting
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- Old Annotation renamed to deprecated LegacyAnnotation
- Annotation is now a trait that can be extended
- New JsonProtocol for Annotation [de]serialization
- Replace AnnotationMap with AnnotationSeq
- Deprecate Transform.getMyAnnotations
- Update Transforms
- Turn on deprecation warnings
- Remove deprecated Driver.compile
- Make AnnotationTests abstract with Legacy and Json subclasses
- Add functionality to convert LegacyAnnotations of built-in annos
This will give a noisy warning and is more of a best effort than a
robust solution.
Fixes #475 Closes #609
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This makes the API change explicit. Also reintroduce loadAnnotations as
a deprecated function.
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* Add DiGraph sum and DiGraph sum test
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Make DiGraph sum deterministic
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Remove ordered hashes/sets from DiGraphTests
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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but not Emitter. (#717)
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* Changed primops to not accept mixed-type args
* Changed return type of sub of two uints to uint
* Added negative tests
* Removed rocket.fir. Manually changed RocketCore to not mix mul arg types. Added integration tests
* Clarified test description and remove println
* Fixed use of throwInternalError
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* Catch exceptions and convert to internal error.
We need to update the displayed message to incorporate a line number and text to be used for the issue.
* Cleanup exception handling/throwing.
Re-throw expected (or uncorrectable exceptions).
Provide Utils.getThrowable() to get the first (eldest) or last throwable in the chain.
Update tests to conform to FreeSpec protocol.
* Minor cleanup
Admit we've updated some deprecated ScalaTest methods.
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Fixes #700
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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A circuit with a single module would fail to properly compute BV RMQs due
to a divide by zero bug.
This changes the computation of the number of blocks an Euler Tour is
broken up into to be, at minimum, one.
This also changes one of the test cases ("wire with source and sink in the
same module") to exercise this.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Two instances of the same module could collide in counting the number of
instances of each Module. This could lead to constants being propagated
on inputs when it is incorrect to do so.
Fixes #734
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Massive refactoring to WiringTransform with the use of a new EulerTour
class to speed things up via fast least common ancestor (LCA) queries.
Changes include (but are not limited to):
* Use lowest common ancestor when wiring
* Add EulerTour class with naive and Berkman-Vishkin RMQ
* Adds LCA method for Instance Graph
* Enables "Two Sources" using "Top" wiring test as this is now valid
* Remove TopAnnotation from WiringTransform
* Represent WiringTransform sink as `Seq[Named]`
* Remove WiringUtils.countInstances, fix imports
* Support sources under sinks in WiringTransform
* Enable internal module wiring
* Support Wiring of Aggregates
h/t @edcote
fixes #728
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Reviewed-by: Jack Koenig<jack.koenig3@gmail.com>
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Change loadAnnotations to return annotations instead of mutating firrtlOptions
Deprecate implicit annotation file (top.anno) and annotation file override
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The logic around this option was unintuitive and led to silently dropped
annotations.
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[skip formal checks]
Generate nicer name for remove accesses
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Fixes #527
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This resulted in parent modules sometimes being constant proppagated
before a child module. If the child module has a constant driving one of
its outputs, the parent module would thus not see the constant. This
resulted in strange unstable constant propagation behavior where
sometimes constant outputs would not propagate.
Also add test illustrating why this occurs with uses of InstanceGraph
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Fixes #708
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This transform replaces all wires with nodes in a legal, flow-forward
order
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Defined as the range from ' ' to '~' [0x20, 0x7e]
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This prevents collisions for one prefix (including temp) from
incrementing the suffix for other prefixes. Makes names more stable.
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Refactor StringLit to use String instead of Array[Byte]
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Adds programArgs to commonOptions
programArgs is all arguments on command line with out leading -/+
or are not bound to a flag.
Create simple test
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Since InstanceGraph now has all modules in its graph, test ConstProp on all modules as a default behaviour.
- Need to think about how to target ConstProp only for a specific module?
Close #644
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* Reorder port and wire assignments in Verilog
* Fixed up syntax
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instantiated multiple times (#634)
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