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authorJack Koenig2018-03-28 12:52:11 -0700
committerGitHub2018-03-28 12:52:11 -0700
commit396ee7ca63eb8a9e201dcdea965cbfc3e9d36783 (patch)
treefe9b57e3153822ec4b78a781c44c75033f1f4e62 /src/test
parentfd8feb55cfa55e2c270d11c1a6ae60ba1950be59 (diff)
Enhance RenameMap to support circuit renaming (#775)
Also delete CircuitTopName. It will not work with updated RenameMap
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/RenameMapSpec.scala42
1 files changed, 42 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/RenameMapSpec.scala b/src/test/scala/firrtlTests/RenameMapSpec.scala
index 9d19bb72..9e305b70 100644
--- a/src/test/scala/firrtlTests/RenameMapSpec.scala
+++ b/src/test/scala/firrtlTests/RenameMapSpec.scala
@@ -3,7 +3,9 @@
package firrtlTests
import firrtl.RenameMap
+import firrtl.FIRRTLException
import firrtl.annotations.{
+ Named,
CircuitName,
ModuleName,
ComponentName
@@ -11,9 +13,13 @@ import firrtl.annotations.{
class RenameMapSpec extends FirrtlFlatSpec {
val cir = CircuitName("Top")
+ val cir2 = CircuitName("Pot")
+ val cir3 = CircuitName("Cir3")
val modA = ModuleName("A", cir)
+ val modA2 = ModuleName("A", cir2)
val modB = ModuleName("B", cir)
val foo = ComponentName("foo", modA)
+ val foo2 = ComponentName("foo", modA2)
val bar = ComponentName("bar", modA)
val fizz = ComponentName("fizz", modA)
val fooB = ComponentName("foo", modB)
@@ -71,4 +77,40 @@ class RenameMapSpec extends FirrtlFlatSpec {
renames.rename(foo, bar)
renames.get(foo) should be (Some(Seq(barB)))
}
+
+ it should "rename modules if their circuit is renamed" in {
+ val renames = RenameMap()
+ renames.rename(cir, cir2)
+ renames.get(modA) should be (Some(Seq(modA2)))
+ }
+
+ it should "rename components if their circuit is renamed" in {
+ val renames = RenameMap()
+ renames.rename(cir, cir2)
+ renames.get(foo) should be (Some(Seq(foo2)))
+ }
+
+ // Renaming `from` to each of the `tos` at the same time should error
+ case class BadRename(from: Named, tos: Seq[Named])
+ val badRenames =
+ Seq(BadRename(foo, Seq(cir)),
+ BadRename(foo, Seq(modA)),
+ BadRename(modA, Seq(foo)),
+ BadRename(modA, Seq(cir)),
+ BadRename(cir, Seq(foo)),
+ BadRename(cir, Seq(modA)),
+ BadRename(cir, Seq(cir2, cir3))
+ )
+ // Run all BadRename tests
+ for (BadRename(from, tos) <- badRenames) {
+ val fromN = from.getClass.getSimpleName
+ val tosN = tos.map(_.getClass.getSimpleName).mkString(", ")
+ it should s"error if a $fromN is renamed to $tosN" in {
+ val renames = RenameMap()
+ for (to <- tos) { renames.rename(from, to) }
+ a [FIRRTLException] shouldBe thrownBy {
+ renames.get(foo)
+ }
+ }
+ }
}