Change primop arg type (#587)

* Changed primops to not accept mixed-type args

* Changed return type of sub of two uints to uint

* Added negative tests

* Removed rocket.fir. Manually changed RocketCore to not mix mul arg types. Added integration tests

* Clarified test description and remove println

* Fixed use of throwInternalError

3 files changed, 49 insertions, 43 deletions

diff --git a/src/test/scala/firrtlTests/IntegrationSpec.scala b/src/test/scala/firrtlTests/IntegrationSpec.scala
index 647aa91b..54923be9 100644
--- a/src/test/scala/firrtlTests/IntegrationSpec.scala
+++ b/src/test/scala/firrtlTests/IntegrationSpec.scala
@@ -48,6 +48,8 @@ class GCDSplitEmissionExecutionTest extends FirrtlFlatSpec {
   }
 }
 
-class RocketCompilationTest extends CompilationTest("rocket", "/regress")
-class BOOMRobCompilationTest extends CompilationTest("Rob", "/regress")
+class RobCompilationTest extends CompilationTest("Rob", "/regress")
+class RocketCoreCompilationTest extends CompilationTest("RocketCore", "/regress")
+class ICacheCompilationTest extends CompilationTest("ICache", "/regress")
+class FPUCompilationTest extends CompilationTest("FPU", "/regress")
 
diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala
index 770c2785..d1d02ee2 100644
--- a/src/test/scala/firrtlTests/WidthSpec.scala
+++ b/src/test/scala/firrtlTests/WidthSpec.scala
@@ -22,42 +22,6 @@ class WidthSpec extends FirrtlFlatSpec {
     }
   }
 
-  "Add of UInt<2> and SInt<2>" should "return SInt<4>" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm,
-      ResolveKinds,
-      InferTypes,
-      CheckTypes,
-      InferWidths)
-    val input =
-      """circuit Unit :
-        |  module Unit :
-        |    input x: UInt<2>
-        |    input y: SInt<2>
-        |    output z: SInt
-        |    z <= add(x, y)""".stripMargin
-    val check = Seq( "output z : SInt<4>")
-    executeTest(input, check, passes)
-  }
-  "SInt<2> - UInt<3>" should "return SInt<5>" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm,
-      ResolveKinds,
-      InferTypes,
-      CheckTypes,
-      InferWidths)
-    val input =
-      """circuit Unit :
-        |  module Unit :
-        |    input x: UInt<3>
-        |    input y: SInt<2>
-        |    output z: SInt
-        |    z <= sub(y, x)""".stripMargin
-    val check = Seq( "output z : SInt<5>")
-    executeTest(input, check, passes)
-  }
   "Dshl by 20 bits" should "result in an error" in {
     val passes = Seq(
       ToWorkingIR,
@@ -121,4 +85,46 @@ class WidthSpec extends FirrtlFlatSpec {
       executeTest(input, Nil, passes)
     }
   }
+
+  "Add of UInt<2> and SInt<2>" should "error" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes,
+      InferWidths)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    input x: UInt<2>
+        |    input y: SInt<2>
+        |    output z: SInt
+        |    z <= add(x, y)""".stripMargin
+    val check = Seq( "output z : SInt<4>")
+    intercept[PassExceptions] {
+      executeTest(input, check, passes)
+    }
+  }
+
+  "SInt<2> - UInt<3>" should "error" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes,
+      InferWidths)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    input x: UInt<3>
+        |    input y: SInt<2>
+        |    output z: SInt
+        |    z <= sub(y, x)""".stripMargin
+    val check = Seq( "output z : SInt<5>")
+    intercept[PassExceptions] {
+      executeTest(input, check, passes)
+    }
+  }
 }
diff --git a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
index 37209786..a866836f 100644
--- a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
@@ -197,12 +197,11 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
         |  module Unit :
         |    input a : Fixed<10><<2>>
         |    input b : Fixed<7><<3>>
-        |    input c : UInt<2>
         |    output cat : UInt
         |    output head : UInt
         |    output tail : UInt
         |    output bits : UInt
-        |    cat <= cat(a, c)
+        |    cat <= cat(a, b)
         |    head <= head(a, 3)
         |    tail <= tail(a, 3)
         |    bits <= bits(a, 6, 3)""".stripMargin
@@ -211,12 +210,11 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
         |  module Unit :
         |    input a : Fixed<10><<2>>
         |    input b : Fixed<7><<3>>
-        |    input c : UInt<2>
-        |    output cat : UInt<12>
+        |    output cat : UInt<17>
         |    output head : UInt<3>
         |    output tail : UInt<7>
         |    output bits : UInt<4>
-        |    cat <= cat(a, c)
+        |    cat <= cat(a, b)
         |    head <= head(a, 3)
         |    tail <= tail(a, 3)
         |    bits <= bits(a, 6, 3)""".stripMargin