diff options
| author | Jack Koenig | 2018-02-27 18:07:11 -0800 |
|---|---|---|
| committer | GitHub | 2018-02-27 18:07:11 -0800 |
| commit | c7eb1570dfb1c7701ea32d1209982a053f3cec1d (patch) | |
| tree | 3f509b202d82841c5dad5588d1f953a25d389b44 /src/test | |
| parent | b90fc784a1819c1d7905910130a7da022214bc22 (diff) | |
Refactor Annotations (#721)
- Old Annotation renamed to deprecated LegacyAnnotation
- Annotation is now a trait that can be extended
- New JsonProtocol for Annotation [de]serialization
- Replace AnnotationMap with AnnotationSeq
- Deprecate Transform.getMyAnnotations
- Update Transforms
- Turn on deprecation warnings
- Remove deprecated Driver.compile
- Make AnnotationTests abstract with Legacy and Json subclasses
- Add functionality to convert LegacyAnnotations of built-in annos
This will give a noisy warning and is more of a best effort than a
robust solution.
Fixes #475 Closes #609
Diffstat (limited to 'src/test')
20 files changed, 397 insertions, 230 deletions
diff --git a/src/test/resources/annotations/InvalidLegacyAnnotations.anno b/src/test/resources/annotations/InvalidLegacyAnnotations.anno new file mode 100644 index 00000000..75bb3b96 --- /dev/null +++ b/src/test/resources/annotations/InvalidLegacyAnnotations.anno @@ -0,0 +1,26 @@ +- targetString: CircuitTop + transformClass: firrtl.VerilogEmitter + value: emitCircuit +- targetString: CircuitTop + transformClass: firrtl.VerilogEmitter + value: emitAllModules +- targetString: CircuitTop + transformClass: firrtl.Transform + value: emittedFirrtlCircuit:0 +- targetString: CircuitTop + transformClass: firrtl.Transform + value: emittedVerilogCircuit:0 +- targetString: CircuitTop + transformClass: firrtl.Transform + value: emittedFirrtlModule:0 +- targetString: CircuitTop + transformClass: firrtl.Transform + value: emittedVerilogModule:0 +- targetString: foo + transformClass: firrtl.Transform + value: | + DELETED by DeadCodeElimination + targetString: foo + transformClass: firrtl.passes.InlineInstances + value: '' + diff --git a/src/test/resources/annotations/LegacyAnnotations.anno b/src/test/resources/annotations/LegacyAnnotations.anno new file mode 100644 index 00000000..395fa56d --- /dev/null +++ b/src/test/resources/annotations/LegacyAnnotations.anno @@ -0,0 +1,50 @@ +- targetString: foo + transformClass: firrtl.passes.InlineInstances + value: '' +- targetString: foo.bar + transformClass: firrtl.passes.clocklist.ClockListTransform + value: output +- targetString: foo + transformClass: firrtl.passes.memlib.InferReadWrite + value: '' +- targetString: foo + transformClass: firrtl.passes.memlib.ReplSeqMem + value: input output +- targetString: foo.bar.x + transformClass: firrtl.passes.memlib.ResolveMemoryReference + value: nodedupmem! +- targetString: foo.bar + transformClass: firrtl.transforms.DedupModules + value: nodedup! +- targetString: foo.bar.x + transformClass: firrtl.passes.wiring.WiringTransform + value: source pin +- targetString: foo.bar.x + transformClass: firrtl.passes.wiring.WiringTransform + value: sink pin +- targetString: foo.bar + transformClass: firrtl.transforms.BlackBoxSourceHelper + value: |- + resource + resource +- targetString: foo.bar + transformClass: firrtl.transforms.BlackBoxSourceHelper + value: |- + inline + name + text +- targetString: foo.bar + transformClass: firrtl.transforms.BlackBoxSourceHelper + value: |- + targetDir + targetdir +- targetString: CircuitTop + transformClass: firrtl.transforms.DeadCodeElimination + value: noDCE! +- targetString: foo.bar.x + transformClass: firrtl.Transform + value: DONTtouch! +- targetString: foo.bar + transformClass: firrtl.Transform + value: optimizableExtModule! + diff --git a/src/test/resources/annotations/SampleAnnotations.anno.json b/src/test/resources/annotations/SampleAnnotations.anno.json new file mode 100644 index 00000000..e4d912a2 --- /dev/null +++ b/src/test/resources/annotations/SampleAnnotations.anno.json @@ -0,0 +1,39 @@ +[ + { + "class":"firrtl.passes.InlineAnnotation", + "target":"Top.Foo" + }, + { + "class":"firrtl.passes.InlineAnnotation", + "target":"Top.Bar" + }, + { + "class":"firrtl.passes.InlineAnnotation", + "target":"Top.Foo.x" + }, + { + "class":"firrtl.passes.InlineAnnotation", + "target":"Top.Foo.y" + }, + { + "class":"firrtl.passes.InlineAnnotation", + "target":"Top" + }, + { + "class":"firrtl.passes.InlineAnnotation", + "target":"OtherTop" + }, + { + "class":"firrtl.passes.InlineAnnotation", + "target":"OtherTop.Foo.x" + }, + { + "class":"firrtl.passes.InlineAnnotation", + "target":"OtherTop.Bar" + }, + { + "class":"firrtl.passes.InlineAnnotation", + "target":"OtherTop.Foo.y" + } +] + diff --git a/src/test/scala/firrtlTests/AnnotationTests.scala b/src/test/scala/firrtlTests/AnnotationTests.scala index 7b7e7839..85814713 100644 --- a/src/test/scala/firrtlTests/AnnotationTests.scala +++ b/src/test/scala/firrtlTests/AnnotationTests.scala @@ -25,32 +25,22 @@ trait AnnotationSpec extends LowTransformSpec { // Check if Annotation Exception is thrown override def failingexecute(input: String, annotations: Seq[Annotation]): Exception = { intercept[AnnotationException] { - compile(CircuitState(parse(input), ChirrtlForm, Some(AnnotationMap(annotations))), Seq.empty) + compile(CircuitState(parse(input), ChirrtlForm, annotations), Seq.empty) } } def execute(input: String, check: Annotation, annotations: Seq[Annotation]): Unit = { - val cr = compile(CircuitState(parse(input), ChirrtlForm, Some(AnnotationMap(annotations))), Seq.empty) - cr.annotations.get.annotations should contain (check) + val cr = compile(CircuitState(parse(input), ChirrtlForm, annotations), Seq.empty) + cr.annotations.toSeq should contain (check) } } +// Abstract but with lots of tests defined so that we can use the same tests +// for Legacy and newer Annotations +abstract class AnnotationTests extends AnnotationSpec with Matchers { + def anno(s: String, value: String ="this is a value", mod: String = "Top"): Annotation + def manno(mod: String): Annotation -/** - * Tests for Annotation Permissibility and Tenacity - * - * WARNING(izraelevitz): Not a complete suite of tests, requires the LowerTypes - * pass and ConstProp pass to correctly populate its RenameMap before Strict, Rigid, Firm, - * Unstable, Fickle, and Insistent can be tested. - */ -class AnnotationTests extends AnnotationSpec with Matchers { - def getAMap(a: Annotation): Option[AnnotationMap] = Some(AnnotationMap(Seq(a))) - def getAMap(as: Seq[Annotation]): Option[AnnotationMap] = Some(AnnotationMap(as)) - def anno(s: String, value: String ="this is a value", mod: String = "Top"): Annotation = - Annotation(ComponentName(s, ModuleName(mod, CircuitName("Top"))), classOf[Transform], value) - def manno(mod: String): Annotation = - Annotation(ModuleName(mod, CircuitName("Top")), classOf[Transform], "some value") - - "Loose and Sticky annotation on a node" should "pass through" in { + "Annotation on a node" should "pass through" in { val input: String = """circuit Top : | module Top : @@ -61,71 +51,6 @@ class AnnotationTests extends AnnotationSpec with Matchers { execute(input, ta, Seq(ta)) } - "Annotations" should "be readable from file" in { - val annotationStream = getClass.getResourceAsStream("/annotations/SampleAnnotations.anno") - val annotationsYaml = scala.io.Source.fromInputStream(annotationStream).getLines().mkString("\n").parseYaml - val annotationArray = annotationsYaml.convertTo[Array[Annotation]] - annotationArray.length should be (9) - annotationArray(0).targetString should be ("ModC") - annotationArray(7).transformClass should be ("firrtl.passes.InlineInstances") - val expectedValue = "TopOfDiamond\nWith\nSome new lines" - annotationArray(7).value should be (expectedValue) - } - - "Badly formatted serializations" should "return reasonable error messages" in { - var badYaml = - """ - |- transformClass: firrtl.passes.InlineInstances - | targetString: circuit.module.. - | value: ModC.this params 16 32 - """.stripMargin.parseYaml - - var thrown = intercept[Exception] { - badYaml.convertTo[Array[Annotation]] - } - thrown.getMessage should include ("Illegal component name") - - badYaml = - """ - |- transformClass: firrtl.passes.InlineInstances - | targetString: .circuit.module.component - | value: ModC.this params 16 32 - """.stripMargin.parseYaml - - thrown = intercept[Exception] { - badYaml.convertTo[Array[Annotation]] - } - thrown.getMessage should include ("Illegal circuit name") - } - - "Round tripping annotations through text file" should "preserve annotations" in { - val annos: Array[Annotation] = Seq( - InlineAnnotation(CircuitName("fox")), - InlineAnnotation(ModuleName("dog", CircuitName("bear"))), - InlineAnnotation(ComponentName("chocolate", ModuleName("like", CircuitName("i")))), - PinAnnotation(CircuitName("Pinniped"), Seq("sea-lion", "monk-seal")) - ).toArray - - val annoFile = new File("temp-anno") - val writer = new FileWriter(annoFile) - writer.write(annos.toYaml.prettyPrint) - writer.close() - - val yaml = io.Source.fromFile(annoFile).getLines().mkString("\n").parseYaml - annoFile.delete() - - val readAnnos = yaml.convertTo[Array[Annotation]] - - annos.zip(readAnnos).foreach { case (beforeAnno, afterAnno) => - beforeAnno.targetString should be (afterAnno.targetString) - beforeAnno.target should be (afterAnno.target) - beforeAnno.transformClass should be (afterAnno.transformClass) - beforeAnno.transform should be (afterAnno.transform) - - beforeAnno should be (afterAnno) - } - } - "Deleting annotations" should "create a DeletedAnnotation" in { val compiler = new VerilogCompiler val input = @@ -136,12 +61,15 @@ class AnnotationTests extends AnnotationSpec with Matchers { class DeletingTransform extends Transform { val inputForm = LowForm val outputForm = LowForm - def execute(state: CircuitState) = state.copy(annotations = None) + def execute(state: CircuitState) = state.copy(annotations = Seq()) } + val transform = new DeletingTransform + val tname = transform.name val inlineAnn = InlineAnnotation(CircuitName("Top")) - val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, getAMap(inlineAnn)), Seq(new DeletingTransform)) - result.annotations.get.annotations.head should matchPattern { - case DeletedAnnotation(x, inlineAnn) => + val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, Seq(inlineAnn)), Seq(transform)) + println(result.annotations.head) + result.annotations.head should matchPattern { + case DeletedAnnotation(`tname`, `inlineAnn`) => } val exception = (intercept[FIRRTLException] { result.getEmittedCircuit @@ -149,6 +77,7 @@ class AnnotationTests extends AnnotationSpec with Matchers { val deleted = result.deletedAnnotations exception.str should be (s"No EmittedCircuit found! Did you delete any annotations?\n$deleted") } + "Renaming" should "propagate in Lowering of memories" in { val compiler = new VerilogCompiler // Uncomment to help debugging failing tests @@ -170,8 +99,8 @@ class AnnotationTests extends AnnotationSpec with Matchers { |""".stripMargin val annos = Seq(anno("m.r.data.b", "sub"), anno("m.r.data", "all"), anno("m", "mem"), dontTouch("Top.m")) - val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, getAMap(annos)), Nil) - val resultAnno = result.annotations.get.annotations + val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil) + val resultAnno = result.annotations.toSeq resultAnno should contain (anno("m_a", "mem")) resultAnno should contain (anno("m_b_0", "mem")) resultAnno should contain (anno("m_b_1", "mem")) @@ -185,7 +114,6 @@ class AnnotationTests extends AnnotationSpec with Matchers { } "Renaming" should "propagate in RemoveChirrtl and Lowering of memories" in { val compiler = new VerilogCompiler - Logger.setClassLogLevels(Map(compiler.getClass.getName -> LogLevel.Debug)) val input = """circuit Top : | module Top : @@ -195,8 +123,8 @@ class AnnotationTests extends AnnotationSpec with Matchers { | read mport r = m[in], clk |""".stripMargin val annos = Seq(anno("r.b", "sub"), anno("r", "all"), anno("m", "mem"), dontTouch("Top.m")) - val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, getAMap(annos)), Nil) - val resultAnno = result.annotations.get.annotations + val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil) + val resultAnno = result.annotations.toSeq resultAnno should contain (anno("m_a", "mem")) resultAnno should contain (anno("m_b_0", "mem")) resultAnno should contain (anno("m_b_1", "mem")) @@ -225,8 +153,8 @@ class AnnotationTests extends AnnotationSpec with Matchers { |""".stripMargin val annos = Seq(anno("zero"), anno("x.a"), anno("x.b"), anno("y[0]"), anno("y[1]"), anno("y[2]"), dontTouch("Top.x")) - val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, getAMap(annos)), Nil) - val resultAnno = result.annotations.get.annotations + val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil) + val resultAnno = result.annotations.toSeq resultAnno should contain (anno("x_a")) resultAnno should not contain (anno("zero")) resultAnno should not contain (anno("x.a")) @@ -267,8 +195,8 @@ class AnnotationTests extends AnnotationSpec with Matchers { anno("write.a"), anno("write.b[0]"), anno("write.b[1]"), dontTouch("Top.r"), dontTouch("Top.w") ) - val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, getAMap(annos)), Nil) - val resultAnno = result.annotations.get.annotations + val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil) + val resultAnno = result.annotations.toSeq resultAnno should not contain (anno("in.a")) resultAnno should not contain (anno("in.b[0]")) resultAnno should not contain (anno("in.b[1]")) @@ -321,8 +249,8 @@ class AnnotationTests extends AnnotationSpec with Matchers { |""".stripMargin val annos = Seq(anno("in"), anno("out"), anno("w"), anno("n"), anno("r"), dontTouch("Top.r"), dontTouch("Top.w")) - val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, getAMap(annos)), Nil) - val resultAnno = result.annotations.get.annotations + val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil) + val resultAnno = result.annotations.toSeq resultAnno should contain (anno("in_a")) resultAnno should contain (anno("in_b_0")) resultAnno should contain (anno("in_b_1")) @@ -357,8 +285,8 @@ class AnnotationTests extends AnnotationSpec with Matchers { |""".stripMargin val annos = Seq(anno("in.b"), anno("out.b"), anno("w.b"), anno("n.b"), anno("r.b"), dontTouch("Top.r"), dontTouch("Top.w")) - val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, getAMap(annos)), Nil) - val resultAnno = result.annotations.get.annotations + val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil) + val resultAnno = result.annotations.toSeq resultAnno should contain (anno("in_b_0")) resultAnno should contain (anno("in_b_1")) resultAnno should contain (anno("out_b_0")) @@ -388,8 +316,8 @@ class AnnotationTests extends AnnotationSpec with Matchers { anno("out.a"), anno("out.b[0]"), anno("out.b[1]"), anno("n.a"), anno("n.b[0]"), anno("n.b[1]") ) - val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, getAMap(annos)), Nil) - val resultAnno = result.annotations.get.annotations + val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil) + val resultAnno = result.annotations.toSeq resultAnno should not contain (anno("in.a")) resultAnno should not contain (anno("in.b[0]")) resultAnno should not contain (anno("in.b[1]")) @@ -438,17 +366,17 @@ class AnnotationTests extends AnnotationSpec with Matchers { anno("foo", mod = "Dead"), anno("bar", mod = "Dead"), anno("foo", mod = "DeadExt"), anno("bar", mod = "DeadExt") ) - val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, getAMap(annos)), Nil) + val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil) /* Uncomment to help debug println(result.circuit.serialize) - result.annotations.get.annotations.foreach{ a => + result.annotations.foreach{ a => a match { case DeletedAnnotation(xform, anno) => println(s"$xform deleted: ${a.target}") case Annotation(target, _, _) => println(s"not deleted: $target") } } */ - val resultAnno = result.annotations.get.annotations + val resultAnno = result.annotations.toSeq resultAnno should contain (manno("Top")) resultAnno should contain (anno("foo", mod = "Top")) @@ -488,8 +416,8 @@ class AnnotationTests extends AnnotationSpec with Matchers { val annos = Seq( anno("x", mod = "Child"), anno("y", mod = "Child_1"), manno("Child"), manno("Child_1") ) - val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, getAMap(annos)), Nil) - val resultAnno = result.annotations.get.annotations + val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil) + val resultAnno = result.annotations.toSeq resultAnno should contain (anno("x", mod = "Child")) resultAnno should contain (anno("y", mod = "Child")) resultAnno should contain (manno("Child")) @@ -503,3 +431,83 @@ class AnnotationTests extends AnnotationSpec with Matchers { require(x == y) } } + +class LegacyAnnotationTests extends AnnotationTests { + def anno(s: String, value: String ="this is a value", mod: String = "Top"): Annotation = + Annotation(ComponentName(s, ModuleName(mod, CircuitName("Top"))), classOf[Transform], value) + def manno(mod: String): Annotation = + Annotation(ModuleName(mod, CircuitName("Top")), classOf[Transform], "some value") + + "LegacyAnnotations" should "be readable from file" in { + val annotationStream = getClass.getResourceAsStream("/annotations/SampleAnnotations.anno") + val annotationsYaml = scala.io.Source.fromInputStream(annotationStream).getLines().mkString("\n").parseYaml + val annotationArray = annotationsYaml.convertTo[Array[LegacyAnnotation]] + annotationArray.length should be (9) + annotationArray(0).targetString should be ("ModC") + annotationArray(7).transformClass should be ("firrtl.passes.InlineInstances") + val expectedValue = "TopOfDiamond\nWith\nSome new lines" + annotationArray(7).value should be (expectedValue) + } + + "Badly formatted LegacyAnnotation serializations" should "return reasonable error messages" in { + var badYaml = + """ + |- transformClass: firrtl.passes.InlineInstances + | targetString: circuit.module.. + | value: ModC.this params 16 32 + """.stripMargin.parseYaml + + var thrown = intercept[Exception] { + badYaml.convertTo[Array[LegacyAnnotation]] + } + thrown.getMessage should include ("Illegal component name") + + badYaml = + """ + |- transformClass: firrtl.passes.InlineInstances + | targetString: .circuit.module.component + | value: ModC.this params 16 32 + """.stripMargin.parseYaml + + thrown = intercept[Exception] { + badYaml.convertTo[Array[LegacyAnnotation]] + } + thrown.getMessage should include ("Illegal circuit name") + } +} + +class JsonAnnotationTests extends AnnotationTests { + // Helper annotations + case class SimpleAnno(target: ComponentName, value: String) extends + SingleTargetAnnotation[ComponentName] { + def duplicate(n: ComponentName) = this.copy(target = n) + } + case class ModuleAnno(target: ModuleName) extends SingleTargetAnnotation[ModuleName] { + def duplicate(n: ModuleName) = this.copy(target = n) + } + + def anno(s: String, value: String ="this is a value", mod: String = "Top"): SimpleAnno = + SimpleAnno(ComponentName(s, ModuleName(mod, CircuitName("Top"))), value) + def manno(mod: String): Annotation = ModuleAnno(ModuleName(mod, CircuitName("Top"))) + + "Round tripping annotations through text file" should "preserve annotations" in { + val annos: Array[Annotation] = Seq( + InlineAnnotation(CircuitName("fox")), + InlineAnnotation(ModuleName("dog", CircuitName("bear"))), + InlineAnnotation(ComponentName("chocolate", ModuleName("like", CircuitName("i")))), + PinAnnotation(Seq("sea-lion", "monk-seal")) + ).toArray + + val annoFile = new File("temp-anno") + val writer = new FileWriter(annoFile) + writer.write(JsonProtocol.serialize(annos)) + writer.close() + + val text = io.Source.fromFile(annoFile).getLines().mkString("\n") + annoFile.delete() + + val readAnnos = JsonProtocol.deserializeTry(text).get + + annos should be (readAnnos) + } +} diff --git a/src/test/scala/firrtlTests/CInferMDirSpec.scala b/src/test/scala/firrtlTests/CInferMDirSpec.scala index 299142d9..a0f55794 100644 --- a/src/test/scala/firrtlTests/CInferMDirSpec.scala +++ b/src/test/scala/firrtlTests/CInferMDirSpec.scala @@ -68,8 +68,7 @@ circuit foo : bar <= io.in """.stripMargin - val annotationMap = AnnotationMap(Nil) - val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotationMap))) + val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm)) // Check correctness of firrtl parse(res.getEmittedCircuit.value) } diff --git a/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala b/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala index 6c8a2f20..06cbb8e4 100644 --- a/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala +++ b/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala @@ -45,7 +45,7 @@ class CheckCombLoopsSpec extends SimpleTransformSpec { |""".stripMargin val writer = new java.io.StringWriter - compile(CircuitState(parse(input), ChirrtlForm, None), writer) + compile(CircuitState(parse(input), ChirrtlForm), writer) } "Simple combinational loop" should "throw an exception" in { @@ -66,7 +66,7 @@ class CheckCombLoopsSpec extends SimpleTransformSpec { val writer = new java.io.StringWriter intercept[CheckCombLoops.CombLoopException] { - compile(CircuitState(parse(input), ChirrtlForm, None), writer) + compile(CircuitState(parse(input), ChirrtlForm), writer) } } @@ -87,7 +87,7 @@ class CheckCombLoopsSpec extends SimpleTransformSpec { val writer = new java.io.StringWriter intercept[CheckCombLoops.CombLoopException] { - compile(CircuitState(parse(input), ChirrtlForm, None), writer) + compile(CircuitState(parse(input), ChirrtlForm), writer) } } @@ -119,7 +119,7 @@ class CheckCombLoopsSpec extends SimpleTransformSpec { val writer = new java.io.StringWriter intercept[CheckCombLoops.CombLoopException] { - compile(CircuitState(parse(input), ChirrtlForm, None), writer) + compile(CircuitState(parse(input), ChirrtlForm), writer) } } @@ -147,7 +147,7 @@ class CheckCombLoopsSpec extends SimpleTransformSpec { val writer = new java.io.StringWriter intercept[CheckCombLoops.CombLoopException] { - compile(CircuitState(parse(input), ChirrtlForm, None), writer) + compile(CircuitState(parse(input), ChirrtlForm), writer) } } @@ -171,7 +171,7 @@ class CheckCombLoopsSpec extends SimpleTransformSpec { val writer = new java.io.StringWriter intercept[CheckCombLoops.CombLoopException] { - compile(CircuitState(parse(input), ChirrtlForm, None), writer) + compile(CircuitState(parse(input), ChirrtlForm), writer) } } } diff --git a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala index d039cc96..74d39286 100644 --- a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala +++ b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala @@ -78,8 +78,7 @@ circuit foo : io.out <= bar """.stripMargin - val annotationMap = AnnotationMap(Nil) - val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotationMap))) + val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm)) // Check correctness of firrtl parse(res.getEmittedCircuit.value) } @@ -104,14 +103,13 @@ circuit foo : io.out <= bar """.stripMargin - val annotationMap = AnnotationMap(Nil) - val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotationMap))) + val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm)) // Check correctness of firrtl parse(res.getEmittedCircuit.value) } ignore should "Memories should not have validif on port clocks when declared in a when" in { - val input = + val input = """;buildInfoPackage: chisel3, version: 3.0-SNAPSHOT, scalaVersion: 2.11.11, sbtVersion: 0.13.16, builtAtString: 2017-10-06 20:55:20.367, builtAtMillis: 1507323320367 |circuit Stack : | module Stack : @@ -157,8 +155,7 @@ circuit foo : | skip @[Stack.scala 19:16] | io.dataOut <= out @[Stack.scala 31:14] """.stripMargin - val annotationMap = AnnotationMap(Nil) - val res = (new LowFirrtlCompiler).compile(CircuitState(parse(input), ChirrtlForm, Some(annotationMap)), Nil).circuit + val res = (new LowFirrtlCompiler).compile(CircuitState(parse(input), ChirrtlForm), Seq()).circuit assert(res search { case Connect(_, WSubField(WSubField(WRef("stack_mem", _, _, _), "_T_35",_, _), "clk", _, _), WRef("clock", _, _, _)) => true case Connect(_, WSubField(WSubField(WRef("stack_mem", _, _, _), "_T_17",_, _), "clk", _, _), WRef("clock", _, _, _)) => true @@ -179,8 +176,7 @@ circuit foo : | read mport bar = mem[addr], clock | out <= bar |""".stripMargin - val annotationMap = AnnotationMap(Nil) - val res = (new LowFirrtlCompiler).compile(CircuitState(parse(input), ChirrtlForm, Some(annotationMap)), Nil).circuit + val res = (new LowFirrtlCompiler).compile(CircuitState(parse(input), ChirrtlForm), Seq()).circuit assert(res search { case Connect(_, WSubField(WSubField(WRef("mem", _, _, _), "bar",_, _), "clk", _, _), WRef("clock", _, _, _)) => true }) @@ -201,8 +197,7 @@ circuit foo : | read mport bar = mem[addr], local | out <= bar |""".stripMargin - val annotationMap = AnnotationMap(Nil) - val res = new LowFirrtlCompiler().compile(CircuitState(parse(input), ChirrtlForm, Some(annotationMap)), Nil).circuit + val res = new LowFirrtlCompiler().compile(CircuitState(parse(input), ChirrtlForm), Seq()).circuit assert(res search { case Connect(_, WSubField(WSubField(WRef("mem", _, _, _), "bar",_, _), "clk", _, _), WRef("clock", _, _, _)) => true }) @@ -223,9 +218,7 @@ circuit foo : | read mport bar = mem[addr], asClock(local) | out <= bar |""".stripMargin - val annotationMap = AnnotationMap(Nil) - - val res = new LowFirrtlCompiler().compile(CircuitState(parse(input), ChirrtlForm, Some(annotationMap)), Nil).circuit + val res = new LowFirrtlCompiler().compile(CircuitState(parse(input), ChirrtlForm), Seq()).circuit assert(res search { case Connect(_, WSubField(WSubField(WRef("mem", _, _, _), "bar",_, _), "clk", _, _), DoPrim(AsClock, Seq(WRef("clock", _, _, _)), Nil, _)) => true }) @@ -246,9 +239,7 @@ circuit foo : | read mport bar = mem[addr], asClock(clock) | out <= bar |""".stripMargin - val annotationMap = AnnotationMap(Nil) - - val res = (new HighFirrtlCompiler).compile(CircuitState(parse(input), ChirrtlForm, Some(annotationMap)), Nil).circuit + val res = (new HighFirrtlCompiler).compile(CircuitState(parse(input), ChirrtlForm), Seq()).circuit assert(res search { case Connect(_, SubField(SubField(Reference("mem", _), "bar", _), "clk", _), DoPrim(AsClock, Seq(Reference("clock", _)), _, _)) => true }) diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala index e28ab432..97c1c146 100644 --- a/src/test/scala/firrtlTests/DCETests.scala +++ b/src/test/scala/firrtlTests/DCETests.scala @@ -20,7 +20,7 @@ class DCETests extends FirrtlFlatSpec { new SimpleTransform(RemoveEmpty, LowForm) ) private def exec(input: String, check: String, annos: Seq[Annotation] = List.empty): Unit = { - val state = CircuitState(parse(input), ChirrtlForm, Some(AnnotationMap(annos))) + val state = CircuitState(parse(input), ChirrtlForm, annos) val finalState = (new LowFirrtlCompiler).compileAndEmit(state, customTransforms) val res = finalState.getEmittedCircuit.value // Convert to sets for comparison diff --git a/src/test/scala/firrtlTests/DriverSpec.scala b/src/test/scala/firrtlTests/DriverSpec.scala index 0327cf8b..406e5f42 100644 --- a/src/test/scala/firrtlTests/DriverSpec.scala +++ b/src/test/scala/firrtlTests/DriverSpec.scala @@ -2,15 +2,32 @@ package firrtlTests -import java.io.File +import java.io.{File, FileWriter} import org.scalatest.{FreeSpec, Matchers} -import firrtl.passes.InlineInstances -import firrtl.passes.memlib.{InferReadWrite, ReplSeqMem} -import firrtl.transforms.BlackBoxSourceHelper +import firrtl.passes.{InlineAnnotation, InlineInstances} +import firrtl.passes.memlib.{ + InferReadWrite, + InferReadWriteAnnotation, + ReplSeqMem, + ReplSeqMemAnnotation +} +import firrtl.transforms.BlackBoxTargetDirAnno import firrtl._ +import firrtl.annotations._ import firrtl.util.BackendCompilationUtilities +class ExceptingTransform extends Transform { + def inputForm = HighForm + def outputForm = HighForm + def execute(state: CircuitState): CircuitState = { + throw new ExceptingTransform.CustomException("I ran!") + } +} +object ExceptingTransform { + case class CustomException(msg: String) extends Exception +} + //noinspection ScalaStyle class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities { "CommonOptions are some simple options available across the chisel3 ecosystem" - { @@ -117,9 +134,7 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities val firrtlOptions = optionsManager.firrtlOptions firrtlOptions.annotations.length should be (3) - firrtlOptions.annotations.foreach { annotation => - annotation.transform shouldBe classOf[InlineInstances] - } + firrtlOptions.annotations.foreach(_ shouldBe an [InlineAnnotation]) } "infer-rw annotation" in { val optionsManager = new ExecutionOptionsManager("test") with HasFirrtlOptions @@ -130,9 +145,7 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities val firrtlOptions = optionsManager.firrtlOptions firrtlOptions.annotations.length should be (1) - firrtlOptions.annotations.foreach { annotation => - annotation.transform shouldBe classOf[InferReadWrite] - } + firrtlOptions.annotations.head should be (InferReadWriteAnnotation) } "repl-seq-mem annotation" in { val optionsManager = new ExecutionOptionsManager("test") with HasFirrtlOptions @@ -143,8 +156,8 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities val firrtlOptions = optionsManager.firrtlOptions firrtlOptions.annotations.length should be (1) - firrtlOptions.annotations.foreach { annotation => - annotation.transform shouldBe classOf[ReplSeqMem] + firrtlOptions.annotations.head should matchPattern { + case ReplSeqMemAnnotation("infile1", "outfile1") => } } } @@ -161,7 +174,7 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities optionsManager.firrtlOptions.annotations.length should be (0) val annos = Driver.getAnnotations(optionsManager) annos.length should be (12) // 9 from circuit plus 3 general purpose - annos.count(_.transformClass == "firrtl.passes.InlineInstances") should be (9) + annos.count(_.isInstanceOf[InlineAnnotation]) should be (9) annoFile.delete() } @@ -178,12 +191,83 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities optionsManager.firrtlOptions.annotations.length should be (0) val annos = Driver.getAnnotations(optionsManager) annos.length should be (12) // 9 from circuit plus 3 general purpose - annos.count(_.transformClass == "firrtl.passes.InlineInstances") should be (9) + annos.count(_.isInstanceOf[InlineAnnotation]) should be (9) annotationsTestFile.delete() } + // Deprecated + "Supported LegacyAnnotations will be converted automagically" in { + val testDir = createTestDirectory("test") + val annoFilename = "LegacyAnnotations.anno" + val annotationsTestFile = new File(testDir, annoFilename) + val optionsManager = new ExecutionOptionsManager("test") with HasFirrtlOptions { + commonOptions = commonOptions.copy(topName = "test", targetDirName = testDir.toString) + firrtlOptions = firrtlOptions.copy( + annotationFileNames = List(annotationsTestFile.toString) + ) + } + copyResourceToFile(s"/annotations/$annoFilename", annotationsTestFile) + val annos = Driver.getAnnotations(optionsManager) + + val cname = CircuitName("foo") + val mname = ModuleName("bar", cname) + val compname = ComponentName("x", mname) + import firrtl.passes.clocklist._ + import firrtl.passes.memlib._ + import firrtl.passes.wiring._ + import firrtl.transforms._ + val expected = List( + InlineAnnotation(cname), + ClockListAnnotation(mname, "output"), + InferReadWriteAnnotation, + ReplSeqMemAnnotation("input", "output"), + NoDedupMemAnnotation(compname), + NoDedupAnnotation(mname), + SourceAnnotation(compname, "pin"), + SinkAnnotation(compname, "pin"), + BlackBoxResourceAnno(mname, "resource"), + BlackBoxInlineAnno(mname, "name", "text"), + BlackBoxTargetDirAnno("targetdir"), + NoDCEAnnotation, + DontTouchAnnotation(compname), + OptimizableExtModuleAnnotation(mname) + ) + for (e <- expected) { + annos should contain (e) + } + } + + // Deprecated + "UNsupported LegacyAnnotations should throw errors" in { + val testDir = createTestDirectory("test") + val annoFilename = "InvalidLegacyAnnotations.anno" + val annotationsTestFile = new File(testDir, annoFilename) + copyResourceToFile(s"/annotations/$annoFilename", annotationsTestFile) + + import net.jcazevedo.moultingyaml._ + val text = io.Source.fromFile(annotationsTestFile).mkString + val yamlAnnos = text.parseYaml match { case YamlArray(xs) => xs } + + // Since each one should error, emit each one to an anno file and try to read it + for ((anno, i) <- yamlAnnos.zipWithIndex) { + val annoFile = new File(testDir, s"anno_$i.anno") + val fw = new FileWriter(annoFile) + fw.write(YamlArray(anno).prettyPrint) + fw.close() + val optionsManager = new ExecutionOptionsManager("test") with HasFirrtlOptions { + commonOptions = commonOptions.copy(topName = "test", targetDirName = testDir.toString) + firrtlOptions = firrtlOptions.copy( + annotationFileNames = List(annoFile.toString) + ) + } + (the [Exception] thrownBy { + Driver.getAnnotations(optionsManager) + }).getMessage should include ("Old-style annotations") + } + } + "Annotations can be read from multiple files" in { - val filename = "SampleAnnotations.anno" + val filename = "SampleAnnotations.anno.json" val optionsManager = new ExecutionOptionsManager("test") with HasFirrtlOptions { commonOptions = commonOptions.copy(topName = "a.fir") firrtlOptions = firrtlOptions.copy( @@ -195,7 +279,7 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities optionsManager.firrtlOptions.annotations.length should be (0) val annos = Driver.getAnnotations(optionsManager) annos.length should be (21) // 18 from files plus 3 general purpose - annos.count(_.transformClass == "firrtl.passes.InlineInstances") should be (18) + annos.count(_.isInstanceOf[InlineAnnotation]) should be (18) annotationsTestFile.delete() } @@ -208,15 +292,15 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities Array("--infer-rw", "circuit", "-faf", annoFile.toString) ) should be (true) - copyResourceToFile("/annotations/SampleAnnotations.anno", annoFile) + copyResourceToFile("/annotations/SampleAnnotations.anno.json", annoFile) val firrtlOptions = optionsManager.firrtlOptions firrtlOptions.annotations.length should be (1) // infer-rw - val anns = Driver.getAnnotations(optionsManager).groupBy(_.transform) - anns(classOf[BlackBoxSourceHelper]).length should be (1) // built-in to getAnnotations - anns(classOf[InferReadWrite]).length should be (1) // --infer-rw - anns(classOf[InlineInstances]).length should be (9) // annotations file + val anns = Driver.getAnnotations(optionsManager) + anns should contain (BlackBoxTargetDirAnno(".")) // built in to getAnnotations + anns should contain (InferReadWriteAnnotation) // --infer-rw + anns.collect { case a: InlineAnnotation => a }.length should be (9) // annotations file annoFile.delete() } diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala index b71e51e2..861d1745 100644 --- a/src/test/scala/firrtlTests/FirrtlSpec.scala +++ b/src/test/scala/firrtlTests/FirrtlSpec.scala @@ -22,10 +22,10 @@ trait FirrtlRunners extends BackendCompilationUtilities { val cppHarnessResourceName: String = "/firrtl/testTop.cpp" /** Compiles input Firrtl to Verilog */ - def compileToVerilog(input: String, annotations: AnnotationMap = AnnotationMap(Seq.empty)): String = { + def compileToVerilog(input: String, annotations: AnnotationSeq = Seq.empty): String = { val circuit = Parser.parse(input.split("\n").toIterator) val compiler = new VerilogCompiler - val res = compiler.compileAndEmit(CircuitState(circuit, HighForm, Some(annotations))) + val res = compiler.compileAndEmit(CircuitState(circuit, HighForm, annotations)) res.getEmittedCircuit.value } /** Compile a Firrtl file @@ -38,7 +38,7 @@ trait FirrtlRunners extends BackendCompilationUtilities { prefix: String, srcDir: String, customTransforms: Seq[Transform] = Seq.empty, - annotations: AnnotationMap = new AnnotationMap(Seq.empty)): File = { + annotations: AnnotationSeq = Seq.empty): File = { val testDir = createTestDirectory(prefix) copyResourceToFile(s"${srcDir}/${prefix}.fir", new File(testDir, s"${prefix}.fir")) @@ -47,7 +47,7 @@ trait FirrtlRunners extends BackendCompilationUtilities { firrtlOptions = FirrtlExecutionOptions( infoModeName = "ignore", customTransforms = customTransforms, - annotations = annotations.annotations.toList) + annotations = annotations.toList) } firrtl.Driver.execute(optionsManager) @@ -65,7 +65,7 @@ trait FirrtlRunners extends BackendCompilationUtilities { srcDir: String, verilogPrefixes: Seq[String] = Seq.empty, customTransforms: Seq[Transform] = Seq.empty, - annotations: AnnotationMap = new AnnotationMap(Seq.empty)) = { + annotations: AnnotationSeq = Seq.empty) = { val testDir = compileFirrtlTest(prefix, srcDir, customTransforms, annotations) val harness = new File(testDir, s"top.cpp") copyResourceToFile(cppHarnessResourceName, harness) @@ -111,8 +111,7 @@ trait FirrtlMatchers extends Matchers { expected: Seq[String], compiler: Compiler, annotations: Seq[Annotation] = Seq.empty) = { - val annoMap = AnnotationMap(annotations) - val finalState = compiler.compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annoMap))) + val finalState = compiler.compileAndEmit(CircuitState(parse(input), ChirrtlForm, annotations)) val lines = finalState.getEmittedCircuit.value split "\n" map normalized for (e <- expected) { lines should contain (e) diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala index 82c9d65f..34e228be 100644 --- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala +++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala @@ -71,8 +71,8 @@ circuit sram6t : T_5 <= io.wdata """.stripMargin - val annotationMap = AnnotationMap(Seq(memlib.InferReadWriteAnnotation("sram6t"))) - val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotationMap))) + val annos = Seq(memlib.InferReadWriteAnnotation) + val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos)) // Check correctness of firrtl parse(res.getEmittedCircuit.value) } @@ -102,8 +102,8 @@ circuit sram6t : io.dataOut <= _T_22 """.stripMargin - val annotationMap = AnnotationMap(Seq(memlib.InferReadWriteAnnotation("sram6t"))) - val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotationMap))) + val annos = Seq(memlib.InferReadWriteAnnotation) + val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos)) // Check correctness of firrtl parse(res.getEmittedCircuit.value) } @@ -133,9 +133,9 @@ circuit sram6t : T_5 <= io.wdata """.stripMargin - val annotationMap = AnnotationMap(Seq(memlib.InferReadWriteAnnotation("sram6t"))) + val annos = Seq(memlib.InferReadWriteAnnotation) intercept[InferReadWriteCheckException] { - compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(annotationMap))) + compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos)) } } } diff --git a/src/test/scala/firrtlTests/PassTests.scala b/src/test/scala/firrtlTests/PassTests.scala index 6727533e..847643ef 100644 --- a/src/test/scala/firrtlTests/PassTests.scala +++ b/src/test/scala/firrtlTests/PassTests.scala @@ -21,7 +21,7 @@ abstract class SimpleTransformSpec extends FlatSpec with FirrtlMatchers with Com // Executes the test. Call in tests. // annotations cannot have default value because scalatest trait Suite has a default value def execute(input: String, check: String, annotations: Seq[Annotation]): Unit = { - val finalState = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(AnnotationMap(annotations)))) + val finalState = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annotations)) val actual = RemoveEmpty.run(parse(finalState.getEmittedCircuit.value)).serialize val expected = parse(check).serialize logger.debug(actual) @@ -32,7 +32,7 @@ abstract class SimpleTransformSpec extends FlatSpec with FirrtlMatchers with Com // No default to be consistent with execute def failingexecute(input: String, annotations: Seq[Annotation]): Exception = { intercept[PassExceptions] { - compile(CircuitState(parse(input), ChirrtlForm, Some(AnnotationMap(annotations))), Seq.empty) + compile(CircuitState(parse(input), ChirrtlForm, annotations), Seq.empty) } } } diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala index 7cbfeafe..dcc23235 100644 --- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala +++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala @@ -63,8 +63,8 @@ circuit Top : io2.commit_entry.bits.info <- R1 """.stripMargin val confLoc = "ReplSeqMemTests.confTEMP" - val aMap = AnnotationMap(Seq(ReplSeqMemAnnotation("-c:Top:-o:"+confLoc))) - val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(aMap))) + val annos = Seq(ReplSeqMemAnnotation.parse("-c:Top:-o:"+confLoc)) + val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos)) // Check correctness of firrtl println(res.annotations) parse(res.getEmittedCircuit.value) @@ -86,8 +86,8 @@ circuit Top : write mport T_155 = mem[p_address], clock """.stripMargin val confLoc = "ReplSeqMemTests.confTEMP" - val aMap = AnnotationMap(Seq(ReplSeqMemAnnotation("-c:Top:-o:"+confLoc))) - val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(aMap))) + val annos = Seq(ReplSeqMemAnnotation.parse("-c:Top:-o:"+confLoc)) + val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos)) // Check correctness of firrtl parse(res.getEmittedCircuit.value) (new java.io.File(confLoc)).delete() @@ -111,8 +111,8 @@ circuit CustomMemory : skip """.stripMargin val confLoc = "ReplSeqMemTests.confTEMP" - val aMap = AnnotationMap(Seq(ReplSeqMemAnnotation("-c:CustomMemory:-o:"+confLoc))) - val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(aMap))) + val annos = Seq(ReplSeqMemAnnotation.parse("-c:CustomMemory:-o:"+confLoc)) + val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos)) // Check correctness of firrtl parse(res.getEmittedCircuit.value) (new java.io.File(confLoc)).delete() @@ -136,8 +136,8 @@ circuit CustomMemory : skip """.stripMargin val confLoc = "ReplSeqMemTests.confTEMP" - val aMap = AnnotationMap(Seq(ReplSeqMemAnnotation("-c:CustomMemory:-o:"+confLoc))) - val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(aMap))) + val annos = Seq(ReplSeqMemAnnotation.parse("-c:CustomMemory:-o:"+confLoc)) + val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos)) // Check correctness of firrtl parse(res.getEmittedCircuit.value) (new java.io.File(confLoc)).delete() @@ -209,10 +209,10 @@ circuit CustomMemory : skip """ val confLoc = "ReplSeqMemTests.confTEMP" - val aMap = AnnotationMap(Seq( - ReplSeqMemAnnotation("-c:CustomMemory:-o:"+confLoc), - NoDedupMemAnnotation(ComponentName("mem_0", ModuleName("CustomMemory",CircuitName("CustomMemory")))))) - val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(aMap))) + val annos = Seq( + ReplSeqMemAnnotation.parse("-c:CustomMemory:-o:"+confLoc), + NoDedupMemAnnotation(ComponentName("mem_0", ModuleName("CustomMemory",CircuitName("CustomMemory"))))) + val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos)) // Check correctness of firrtl val circuit = parse(res.getEmittedCircuit.value) val numExtMods = circuit.modules.count { @@ -249,10 +249,10 @@ circuit CustomMemory : skip """ val confLoc = "ReplSeqMemTests.confTEMP" - val aMap = AnnotationMap(Seq( - ReplSeqMemAnnotation("-c:CustomMemory:-o:"+confLoc), - NoDedupMemAnnotation(ComponentName("mem_1", ModuleName("CustomMemory",CircuitName("CustomMemory")))))) - val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(aMap))) + val annos = Seq( + ReplSeqMemAnnotation.parse("-c:CustomMemory:-o:"+confLoc), + NoDedupMemAnnotation(ComponentName("mem_1", ModuleName("CustomMemory",CircuitName("CustomMemory"))))) + val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos)) // Check correctness of firrtl val circuit = parse(res.getEmittedCircuit.value) val numExtMods = circuit.modules.count { @@ -285,8 +285,8 @@ circuit CustomMemory : skip """ val confLoc = "ReplSeqMemTests.confTEMP" - val aMap = AnnotationMap(Seq(ReplSeqMemAnnotation("-c:CustomMemory:-o:"+confLoc))) - val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, Some(aMap))) + val annos = Seq(ReplSeqMemAnnotation.parse("-c:CustomMemory:-o:"+confLoc)) + val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos)) // Check correctness of firrtl val circuit = parse(res.getEmittedCircuit.value) val numExtMods = circuit.modules.count { diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala index 018a35f6..a38a8def 100644 --- a/src/test/scala/firrtlTests/UnitTests.scala +++ b/src/test/scala/firrtlTests/UnitTests.scala @@ -24,7 +24,7 @@ class UnitTests extends FirrtlFlatSpec { val c = transforms.foldLeft(CircuitState(parse(input), UnknownForm)) { (c: CircuitState, t: Transform) => t.runTransform(c) }.circuit - CircuitState(c, UnknownForm, None, None) + CircuitState(c, UnknownForm, Seq(), None) } "Pull muxes" should "not be exponential in runtime" in { diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala index 6da73157..4f8fd9fe 100644 --- a/src/test/scala/firrtlTests/WiringTests.scala +++ b/src/test/scala/firrtlTests/WiringTests.scala @@ -705,7 +705,7 @@ class WiringTests extends FirrtlFlatSpec { (c: Circuit, p: Pass) => p.run(c) } val wiringXForm = new WiringTransform() - val retC = wiringXForm.execute(CircuitState(c, MidForm, Some(AnnotationMap(Seq(source, sink))), None)).circuit + val retC = wiringXForm.execute(CircuitState(c, MidForm, Seq(source, sink))).circuit (parse(retC.serialize).serialize) should be (parse(check).serialize) } @@ -743,7 +743,7 @@ class WiringTests extends FirrtlFlatSpec { (c: Circuit, p: Pass) => p.run(c) } val wiringXForm = new WiringTransform() - val retC = wiringXForm.execute(CircuitState(c, MidForm, Some(AnnotationMap(Seq(source, sink))), None)).circuit + val retC = wiringXForm.execute(CircuitState(c, MidForm, Seq(source, sink))).circuit (parse(retC.serialize).serialize) should be (parse(check).serialize) } @@ -789,7 +789,7 @@ class WiringTests extends FirrtlFlatSpec { (c: Circuit, p: Pass) => p.run(c) } val wiringXForm = new WiringTransform() - val retC = wiringXForm.execute(CircuitState(c, MidForm, Some(AnnotationMap(Seq(source, sink))), None)).circuit + val retC = wiringXForm.execute(CircuitState(c, MidForm, Seq(source, sink))).circuit (parse(retC.serialize).serialize) should be (parse(check).serialize) } diff --git a/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala b/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala index 60cbf0fc..eb061d8f 100644 --- a/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala +++ b/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala @@ -14,11 +14,9 @@ class FindTargetDirTransform(expected: String) extends Transform { var run = false def execute(state: CircuitState): CircuitState = { run = true - state.annotations.foreach { aMap => - aMap.annotations.collectFirst { - case TargetDirAnnotation(expected) => - foundTargetDir = true - } + state.annotations.collectFirst { + case TargetDirAnnotation(expected) => + foundTargetDir = true } state } diff --git a/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala b/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala index 39da2a33..a4319e8b 100644 --- a/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala +++ b/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala @@ -2,7 +2,7 @@ package firrtlTests.fixed -import firrtl.{CircuitState, ChirrtlForm, LowFirrtlCompiler, Parser, AnnotationMap} +import firrtl.{CircuitState, ChirrtlForm, LowFirrtlCompiler, Parser} import firrtl.Parser.IgnoreInfo import firrtlTests.FirrtlFlatSpec diff --git a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala index 34a22c26..8645fa62 100644 --- a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala +++ b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala @@ -185,7 +185,7 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec { } val chirrtlTransform = new CheckChirrtlTransform - chirrtlTransform.execute(CircuitState(parse(input), ChirrtlForm, Some(new AnnotationMap(Seq.empty)))) + chirrtlTransform.execute(CircuitState(parse(input), ChirrtlForm)) } "Fixed point numbers" should "remove nested AsFixedPoint" in { diff --git a/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala b/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala index bf294fe9..4c550c46 100644 --- a/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala +++ b/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala @@ -4,39 +4,12 @@ package firrtlTests.transforms import firrtl.annotations.{Annotation, CircuitName, ModuleName} import firrtl.transforms._ -import firrtl.{AnnotationMap, FIRRTLException, Transform, VerilogCompiler} +import firrtl.{FIRRTLException, Transform, VerilogCompiler} import firrtlTests.{HighTransformSpec, LowTransformSpec} import org.scalacheck.Test.Failed import org.scalatest.{FreeSpec, Matchers, Succeeded} -/** - * Tests inline instances transformation - */ -class BlacklBoxSourceHelperSpec extends FreeSpec with Matchers { - "BlackBoxSourceAnnotations" - { - val modName = ModuleName("dog", CircuitName("fox")) - val resource = "file://somefile.v" - - "should parse and unparse" in { - - val serialized = BlackBoxResource(resource).serialize - BlackBoxSource.parse(serialized) match { - case Some(BlackBoxResource(id)) => - id should be (resource) - Succeeded - case _ => Failed - } - } - "should fail on unsupported kinds" in { - intercept[FIRRTLException] { - BlackBoxSourceAnnotation(modName, "bad value") - } - BlackBoxSourceAnnotation(modName, BlackBoxResource(resource).serialize).isInstanceOf[Annotation] should be(true) - } - } -} - class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec { def transform: Transform = new BlackBoxSourceHelper @@ -79,8 +52,8 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec { "annotated external modules" should "appear in output directory" in { val annos = Seq( - Annotation(moduleName, classOf[BlackBoxSourceHelper], BlackBoxTargetDir("test_run_dir").serialize), - Annotation(moduleName, classOf[BlackBoxSourceHelper], BlackBoxResource("/blackboxes/AdderExtModule.v").serialize) + BlackBoxTargetDirAnno("test_run_dir"), + BlackBoxResourceAnno(moduleName, "/blackboxes/AdderExtModule.v") ) execute(input, output, annos) diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala index 74c4b4e7..e88bd506 100644 --- a/src/test/scala/firrtlTests/transforms/DedupTests.scala +++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala @@ -8,7 +8,7 @@ import org.scalatest.Matchers import org.scalatest.junit.JUnitRunner import firrtl.ir.Circuit -import firrtl.{Parser, AnnotationMap} +import firrtl.Parser import firrtl.passes.PassExceptions import firrtl.annotations.{ Named, |