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Remove modName from Module
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Also restrict black boxes to not allow hardware inside of them since it was
being silently dropped anyway.
Resolves #289
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Implemented by adding a Boolean to check for alternating invocations of object
Module.apply and the constructor of abstract class Module.
Fixes #192
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No more need for e.g.
new Bundle {
def foo(dummy: Int): Data
}
as now you can write
new Bundle {
def foo: Data
}
This also removes code duplication with Module.
h/t @sdtwigg
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* FixedPoint number support for chisel3
FixedPoint numbers have a width and a binary position
Either, neither or both maybe inferred.
Firrtl will convert these to SInts during lowering passes
* Fixes based on Jack's comments on PR #328
* Add experimental warning to FixedPoint class and object
* Fixed comment per Adam's comment on PR #328
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Code that imports Chisel._ shouldn't see them.
Not sure if requireIOWrap is the right condition... or if cyan is a
good choice of color for deprecation warnings.
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Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports.
NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence).
We should really thread the CompileOptions through the macro system so the client's implicits are used.
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Additionally, fix Clock.asUInt (previously, it threw an esoteric exception), and add a simple test of both.
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In the Chisel frontend, the implicit clock is named clock, but in the
generated FIRRTL, it is named clk. There is no reason for this
discrepancy, and yet fixing it is painful, as it will break test harnesses.
Better to take the pain now than later.
Resolves #258.
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Printable is a new type that changes how printing of Chisel types is represented
It uses an ordered collection rather than a format string and specifiers
Features:
- Custom String Interpolator for Scala-like printf
- String-like manipulation of "hardware strings" for custom pretty-printing
- Default pretty-printing for Chisel data types
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Eliminate builder compileOptions.
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Stricter values are "true". Current default (not strict) values are "false".
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signalName -> instanceName
SignalId -> InstanceId
Based on Stephen's comments on PR
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"assumeNoDirectionIsInput".
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* signalName: returns the chirrtl name of the signal
* pathName: returns the full path name of the signal from the top module
* parentPathName: returns the full path of the signal's parent module instance from the top module
* parentModName: returns the signal's parent **module(not instance)** name.
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Revive support for firrtl flip direction.
Remove compileOptions.internalConnectionToInputOk
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Assume LHSItOutput if neither side is driving.
Restore Wire()'s removal of direction in binding.
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Nothing uses these now, but when we integrate Stephen's PR200, we'll need a way to selectively enable some strict connection checks on a file by file basis. We plan to do this using package imports which will define suitable compilation options.
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It's not entirely clear what the FIRRTL implementation supports, so
I'm using the ANSI C requirements for the time being.
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