diff options
Diffstat (limited to 'src/test')
56 files changed, 68 insertions, 152 deletions
diff --git a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala index 853d82af..b8a0a5ef 100644 --- a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala +++ b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala @@ -3,12 +3,11 @@ package chiselTests import chisel3._ -import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform} +import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform, annotate} import chisel3.internal.InstanceId import chisel3.testers.BasicTester import firrtl.{CircuitForm, CircuitState, LowForm, Transform} import firrtl.annotations.{ - Annotation, SingleTargetAnnotation, ModuleName, Named diff --git a/src/test/scala/chiselTests/AnnotationNoDedup.scala b/src/test/scala/chiselTests/AnnotationNoDedup.scala index d94cc2fc..3cb457eb 100644 --- a/src/test/scala/chiselTests/AnnotationNoDedup.scala +++ b/src/test/scala/chiselTests/AnnotationNoDedup.scala @@ -3,9 +3,8 @@ package chiselTests import chisel3._ -import chisel3.experimental.{annotate, ChiselAnnotation, doNotDedup} +import chisel3.experimental.doNotDedup import firrtl.FirrtlExecutionSuccess -import firrtl.transforms.NoDedupAnnotation import org.scalatest.{FreeSpec, Matchers} diff --git a/src/test/scala/chiselTests/AsTypeOfTester.scala b/src/test/scala/chiselTests/AsTypeOfTester.scala index 563e2b11..7861f51b 100644 --- a/src/test/scala/chiselTests/AsTypeOfTester.scala +++ b/src/test/scala/chiselTests/AsTypeOfTester.scala @@ -2,12 +2,9 @@ package chiselTests -import org.scalatest._ - import chisel3._ import chisel3.experimental.{DataMirror, FixedPoint, ChiselEnum} import chisel3.testers.BasicTester -import chisel3.util._ class AsTypeOfBundleTester extends BasicTester { class MultiTypeBundle extends Bundle { diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala index fab6f87b..3bea2e4f 100644 --- a/src/test/scala/chiselTests/Assert.scala +++ b/src/test/scala/chiselTests/Assert.scala @@ -2,7 +2,6 @@ package chiselTests -import org.scalatest._ import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ diff --git a/src/test/scala/chiselTests/AutoClonetypeSpec.scala b/src/test/scala/chiselTests/AutoClonetypeSpec.scala index e533eb94..7ab20e5a 100644 --- a/src/test/scala/chiselTests/AutoClonetypeSpec.scala +++ b/src/test/scala/chiselTests/AutoClonetypeSpec.scala @@ -4,8 +4,6 @@ package chiselTests import chisel3._ -import chisel3.testers.BasicTester - class BundleWithIntArg(val i: Int) extends Bundle { val out = UInt(i.W) } diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala index 1b91da3c..0ac28899 100644 --- a/src/test/scala/chiselTests/BetterNamingTests.scala +++ b/src/test/scala/chiselTests/BetterNamingTests.scala @@ -2,11 +2,11 @@ package chiselTests -import collection.mutable - import chisel3._ import chisel3.util._ +import scala.collection.mutable + // Defined outside of the class so we don't get $ in name class Other(w: Int) extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala index 1292222c..505178a4 100644 --- a/src/test/scala/chiselTests/BitwiseOps.scala +++ b/src/test/scala/chiselTests/BitwiseOps.scala @@ -3,8 +3,6 @@ package chiselTests import chisel3._ -import org.scalatest._ -import org.scalatest.prop._ import chisel3.testers.BasicTester class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester { diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala index b45171f4..70ddd4da 100644 --- a/src/test/scala/chiselTests/BlackBox.scala +++ b/src/test/scala/chiselTests/BlackBox.scala @@ -2,14 +2,10 @@ package chiselTests -import java.io.File - -import org.scalatest._ import chisel3._ import chisel3.experimental._ import chisel3.testers.BasicTester import chisel3.util._ -//import chisel3.core.ExplicitCompileOptions.Strict class BlackBoxInverter extends BlackBox { val io = IO(new Bundle() { @@ -176,7 +172,7 @@ class BlackBoxSpec extends ChiselFlatSpec { elaborate(new Module { val io = IO(new Bundle { }) val m = Module(new BlackBoxPassthrough) - assert(chisel3.experimental.DataMirror.modulePorts(m) == Seq( + assert(DataMirror.modulePorts(m) == Seq( "in" -> m.io.in, "out" -> m.io.out)) }) } diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala index 80bea3a0..70bd0166 100644 --- a/src/test/scala/chiselTests/BoringUtilsSpec.scala +++ b/src/test/scala/chiselTests/BoringUtilsSpec.scala @@ -2,8 +2,6 @@ package chiselTests -import java.io.File - import chisel3._ import chisel3.util.Counter import chisel3.testers.BasicTester diff --git a/src/test/scala/chiselTests/BundleLiteralSpec.scala b/src/test/scala/chiselTests/BundleLiteralSpec.scala index 2a6c53d5..aa1dbc0f 100644 --- a/src/test/scala/chiselTests/BundleLiteralSpec.scala +++ b/src/test/scala/chiselTests/BundleLiteralSpec.scala @@ -6,7 +6,7 @@ import chisel3._ import chisel3.testers.BasicTester import chisel3.experimental.RawModule import chisel3.experimental.BundleLiterals._ -import chisel3.core.BundleLiteralException +import chisel3.experimental.BundleLiteralException class BundleLiteralSpec extends ChiselFlatSpec { class MyBundle extends Bundle { diff --git a/src/test/scala/chiselTests/BundleSpec.scala b/src/test/scala/chiselTests/BundleSpec.scala index d30b64b3..c5f40c8a 100644 --- a/src/test/scala/chiselTests/BundleSpec.scala +++ b/src/test/scala/chiselTests/BundleSpec.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.core.IgnoreSeqInBundle import chisel3.testers.BasicTester trait BundleSpecUtils { diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala index 0faab9d0..56a9f1bf 100644 --- a/src/test/scala/chiselTests/BundleWire.scala +++ b/src/test/scala/chiselTests/BundleWire.scala @@ -2,10 +2,7 @@ package chiselTests import chisel3._ -import org.scalatest._ -import org.scalatest.prop._ import chisel3.testers.BasicTester -//import chisel3.core.ExplicitCompileOptions.Strict class Coord extends Bundle { val x = UInt(32.W) diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala index ff75c1a3..0a0eb3f0 100644 --- a/src/test/scala/chiselTests/ChiselSpec.scala +++ b/src/test/scala/chiselTests/ChiselSpec.scala @@ -2,7 +2,6 @@ package chiselTests -import java.io.File import org.scalatest._ import org.scalatest.prop._ import org.scalacheck._ diff --git a/src/test/scala/chiselTests/CloneModuleSpec.scala b/src/test/scala/chiselTests/CloneModuleSpec.scala index bef29fce..59ba2eb5 100644 --- a/src/test/scala/chiselTests/CloneModuleSpec.scala +++ b/src/test/scala/chiselTests/CloneModuleSpec.scala @@ -4,10 +4,8 @@ package chiselTests import chisel3._ import chisel3.util.{Queue, EnqIO, DeqIO, QueueIO, log2Ceil} -import chisel3.experimental.{CloneModuleAsRecord, MultiIOModule} +import chisel3.experimental.{CloneModuleAsRecord, IO, MultiIOModule} import chisel3.testers.BasicTester -import org.scalatest._ -import org.scalatest.prop._ class MultiIOQueue[T <: Data](gen: T, val entries: Int) extends MultiIOModule { val clk = IO(Input(Clock())) diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala index 02b35734..861b3fdd 100644 --- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala @@ -2,7 +2,7 @@ package chiselTests -import collection.immutable.ListMap +import scala.collection.immutable.ListMap // Keep Chisel._ separate from chisel3._ below object CompatibilityComponents { diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala index 57cb5ec3..ac9b6029 100644 --- a/src/test/scala/chiselTests/CompatibilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilitySpec.scala @@ -297,7 +297,7 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks // Note: This is a regression (see https://github.com/freechipsproject/chisel3/issues/668) it should "fail for Chisel types" in { import Chisel._ - an [chisel3.core.Binding.ExpectedHardwareException] should be thrownBy { + an [chisel3.ExpectedHardwareException] should be thrownBy { elaborate(new Module { val io = new Bundle { } UInt(INPUT).dir diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala index 4f647442..10be4ffb 100644 --- a/src/test/scala/chiselTests/CompileOptionsTest.scala +++ b/src/test/scala/chiselTests/CompileOptionsTest.scala @@ -3,13 +3,12 @@ package chiselTests import chisel3._ -import chisel3.core.Binding.BindingException -import chisel3.core.CompileOptions._ +import chisel3.CompileOptions._ class CompileOptionsSpec extends ChiselFlatSpec { - abstract class StrictModule extends Module()(chisel3.core.ExplicitCompileOptions.Strict) - abstract class NotStrictModule extends Module()(chisel3.core.ExplicitCompileOptions.NotStrict) + abstract class StrictModule extends Module()(chisel3.ExplicitCompileOptions.Strict) + abstract class NotStrictModule extends Module()(chisel3.ExplicitCompileOptions.NotStrict) class SmallBundle extends Bundle { val f1 = UInt(4.W) @@ -24,7 +23,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { // scalastyle:off line.size.limit "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [ChiselException] should be thrownBy { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ConnectFieldMismatchModule extends Module { val io = IO(new Bundle { @@ -38,7 +37,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module with missing bundle fields when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { - import chisel3.core.ExplicitCompileOptions.NotStrict + import chisel3.ExplicitCompileOptions.NotStrict class ConnectFieldMismatchModule extends Module { val io = IO(new Bundle { @@ -52,7 +51,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { "A Module in which a Reg is created with a bound type when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [BindingException] should be thrownBy { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class CreateRegFromBoundTypeModule extends Module { val io = IO(new Bundle { @@ -66,7 +65,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module in which a Reg is created with a bound type when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { - import chisel3.core.ExplicitCompileOptions.NotStrict + import chisel3.ExplicitCompileOptions.NotStrict class CreateRegFromBoundTypeModule extends Module { val io = IO(new Bundle { @@ -79,7 +78,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module with wrapped IO when compiled with implicit Strict.CompileOption " should "not throw an exception" in { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class RequireIOWrapModule extends Module { val io = IO(new Bundle { @@ -93,7 +92,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { "A Module with unwrapped IO when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [BindingException] should be thrownBy { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class RequireIOWrapModule extends Module { val io = new Bundle { @@ -110,7 +109,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { "A Module connecting output as source to input as sink when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [ChiselException] should be thrownBy { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class SimpleModule extends Module { val io = IO(new Bundle { @@ -127,7 +126,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module connecting output as source to input as sink when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { - import chisel3.core.ExplicitCompileOptions.NotStrict + import chisel3.ExplicitCompileOptions.NotStrict class SimpleModule extends Module { val io = IO(new Bundle { @@ -145,8 +144,8 @@ class CompileOptionsSpec extends ChiselFlatSpec { "A Module with directionless connections when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [ChiselException] should be thrownBy { // Verify we can suppress the inclusion of default compileOptions - import Chisel.{defaultCompileOptions => _, _} - import chisel3.core.ExplicitCompileOptions.Strict + import Chisel.{defaultCompileOptions => _} + import chisel3.ExplicitCompileOptions.Strict class SimpleModule extends Module { val io = IO(new Bundle { @@ -167,7 +166,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module with directionless connections when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { - import chisel3.core.ExplicitCompileOptions.NotStrict + import chisel3.ExplicitCompileOptions.NotStrict class SimpleModule extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala index 56a7aa3d..d0535ae2 100644 --- a/src/test/scala/chiselTests/ComplexAssign.scala +++ b/src/test/scala/chiselTests/ComplexAssign.scala @@ -2,9 +2,6 @@ package chiselTests -import org.scalatest._ -import org.scalatest.prop._ - import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala index b85d37a1..34fdec8e 100644 --- a/src/test/scala/chiselTests/Counter.scala +++ b/src/test/scala/chiselTests/Counter.scala @@ -2,9 +2,6 @@ package chiselTests -import org.scalatest._ -import org.scalatest.prop._ - import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala index ff6c83b9..59ad6324 100644 --- a/src/test/scala/chiselTests/Decoder.scala +++ b/src/test/scala/chiselTests/Decoder.scala @@ -2,8 +2,6 @@ package chiselTests -import org.scalatest._ -import org.scalatest.prop._ import org.scalacheck._ import chisel3._ diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala index 0b0807fd..4c5e819d 100644 --- a/src/test/scala/chiselTests/Direction.scala +++ b/src/test/scala/chiselTests/Direction.scala @@ -4,7 +4,7 @@ package chiselTests import org.scalatest._ import chisel3._ -import chisel3.util.Decoupled +import chisel3.experimental.RawModule class DirectionedBundle extends Bundle { val in = Input(UInt(32.W)) @@ -128,7 +128,6 @@ class DirectionSpec extends ChiselPropSpec with Matchers { } import chisel3.experimental.{MultiIOModule, DataMirror, Direction, RawModule} - import chisel3.core.SpecifiedDirection property("Directions should be preserved through cloning and binding of Bundles") { elaborate(new MultiIOModule { diff --git a/src/test/scala/chiselTests/DontTouchSpec.scala b/src/test/scala/chiselTests/DontTouchSpec.scala index f916b20a..4b1bce8e 100644 --- a/src/test/scala/chiselTests/DontTouchSpec.scala +++ b/src/test/scala/chiselTests/DontTouchSpec.scala @@ -4,7 +4,6 @@ package chiselTests import chisel3._ import chisel3.experimental.dontTouch -import firrtl.{FirrtlExecutionSuccess, Transform} class HasDeadCodeChild(withDontTouch: Boolean) extends Module { val io = IO(new Bundle { @@ -52,7 +51,7 @@ class DontTouchSpec extends ChiselFlatSpec { } } "Dont touch" should "only work on bound hardware" in { - a [chisel3.core.Binding.BindingException] should be thrownBy { + a [chisel3.BindingException] should be thrownBy { elaborate(new Module { val io = IO(new Bundle { }) dontTouch(new Bundle { val a = UInt(32.W) } ) diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala index db569233..d6bfc94d 100644 --- a/src/test/scala/chiselTests/EnableShiftRegister.scala +++ b/src/test/scala/chiselTests/EnableShiftRegister.scala @@ -2,7 +2,6 @@ package chiselTests import chisel3._ -import chisel3.testers.BasicTester class EnableShiftRegister extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/ExtModule.scala b/src/test/scala/chiselTests/ExtModule.scala index 5d5b51f9..0349d180 100644 --- a/src/test/scala/chiselTests/ExtModule.scala +++ b/src/test/scala/chiselTests/ExtModule.scala @@ -2,17 +2,16 @@ package chiselTests -import java.io.File - -import org.scalatest._ import chisel3._ import chisel3.experimental._ import chisel3.testers.BasicTester -import chisel3.util._ // Avoid collisions with regular BlackBox tests by putting ExtModule blackboxes // in their own scope. package ExtModule { + + import chisel3.experimental.ExtModule + class BlackBoxInverter extends ExtModule { val in = IO(Input(Bool())) val out = IO(Output(Bool())) @@ -72,7 +71,7 @@ class ExtModuleSpec extends ChiselFlatSpec { elaborate(new Module { val io = IO(new Bundle { }) val m = Module(new ExtModule.BlackBoxPassthrough) - assert(chisel3.experimental.DataMirror.modulePorts(m) == Seq( + assert(DataMirror.modulePorts(m) == Seq( "in" -> m.in, "out" -> m.out)) }) } diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala index 499ab591..5c9641be 100644 --- a/src/test/scala/chiselTests/GCD.scala +++ b/src/test/scala/chiselTests/GCD.scala @@ -4,8 +4,6 @@ package chiselTests import chisel3._ import chisel3.testers.BasicTester -import org.scalatest._ -import org.scalatest.prop._ class GCD extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala index 1da3d166..57596b49 100644 --- a/src/test/scala/chiselTests/Harness.scala +++ b/src/test/scala/chiselTests/Harness.scala @@ -2,10 +2,8 @@ package chiselTests -import chisel3.testers.BasicTester -import org.scalatest._ -import org.scalatest.prop._ import java.io.File + import firrtl.util.BackendCompilationUtilities class HarnessSpec extends ChiselPropSpec diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala index af64c9f3..55d9e947 100644 --- a/src/test/scala/chiselTests/IOCompatibility.scala +++ b/src/test/scala/chiselTests/IOCompatibility.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.core.Binding.BindingException import org.scalatest._ class IOCSimpleIO extends Bundle { diff --git a/src/test/scala/chiselTests/InlineSpec.scala b/src/test/scala/chiselTests/InlineSpec.scala index 0bb29fdf..3cc83bb9 100644 --- a/src/test/scala/chiselTests/InlineSpec.scala +++ b/src/test/scala/chiselTests/InlineSpec.scala @@ -4,15 +4,11 @@ package chiselTests import chisel3._ import chisel3.util.experimental.{InlineInstance, FlattenInstance} -import chisel3.internal.firrtl.Circuit import firrtl.FirrtlExecutionSuccess import firrtl.passes.InlineAnnotation -import firrtl.annotations.Annotation import firrtl.transforms.FlattenAnnotation import firrtl.analyses.InstanceGraph import firrtl.{ir => fir} -import firrtl.WDefInstance -import firrtl.Mappers._ import org.scalatest.{FreeSpec, Matchers} class InlineSpec extends FreeSpec with ChiselRunners with Matchers { diff --git a/src/test/scala/chiselTests/InstanceNameSpec.scala b/src/test/scala/chiselTests/InstanceNameSpec.scala index 7bb91b94..afd9af93 100644 --- a/src/test/scala/chiselTests/InstanceNameSpec.scala +++ b/src/test/scala/chiselTests/InstanceNameSpec.scala @@ -4,8 +4,6 @@ package chiselTests import chisel3._ import chisel3.util.Queue -import chisel3.experimental.{DataMirror, FixedPoint} -import chisel3.testers.BasicTester class InstanceNameModule extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/InvalidateAPISpec.scala b/src/test/scala/chiselTests/InvalidateAPISpec.scala index 8dfb078b..a285b4c8 100644 --- a/src/test/scala/chiselTests/InvalidateAPISpec.scala +++ b/src/test/scala/chiselTests/InvalidateAPISpec.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.core.BiConnect.BiConnectException import chisel3.util.Counter import firrtl.passes.CheckInitialization.RefNotInitializedException import firrtl.util.BackendCompilationUtilities @@ -23,7 +22,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila // scalastyle:off line.size.limit property("an output connected to DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithDontCare extends Module { val io = IO(new TrivialInterface) io.out := DontCare @@ -34,7 +33,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should NOT emit a Firrtl \"is invalid\" with Strict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithoutDontCare extends Module { val io = IO(new TrivialInterface) io.out := io.in @@ -44,7 +43,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should emit a Firrtl \"is invalid\" with NotStrict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.NotStrict + import chisel3.ExplicitCompileOptions.NotStrict class ModuleWithoutDontCare extends Module { val io = IO(new TrivialInterface) io.out := io.in @@ -54,7 +53,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("a bundle with a DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithoutDontCare extends Module { val io = IO(new TrivialInterface) io <> DontCare @@ -65,7 +64,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("a Vec with a DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions and bulk connect") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict val nElements = 5 class ModuleWithoutDontCare extends Module { val io = IO(new Bundle { @@ -79,7 +78,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("a Vec with a DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions and mono connect") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict val nElements = 5 class ModuleWithoutDontCare extends Module { val io = IO(new Bundle { @@ -93,7 +92,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("a DontCare cannot be a connection sink (LHS) for := ") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithDontCareSink extends Module { val io = IO(new TrivialInterface) DontCare := io.in @@ -105,7 +104,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("a DontCare cannot be a connection sink (LHS) for <>") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithDontCareSink extends Module { val io = IO(new TrivialInterface) DontCare <> io.in @@ -117,7 +116,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("FIRRTL should complain about partial initialization with Strict CompileOptions and conditional connect") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithIncompleteAssignment extends Module { val io = IO(new Bundle { val out = Output(Bool()) @@ -134,7 +133,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("FIRRTL should not complain about partial initialization with Strict CompileOptions and conditional connect after unconditional connect") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithUnconditionalAssignment extends Module { val io = IO(new Bundle { val out = Output(Bool()) @@ -149,7 +148,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("FIRRTL should not complain about partial initialization with Strict CompileOptions and conditional connect with otherwise clause") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithConditionalAndOtherwiseAssignment extends Module { val io = IO(new Bundle { val out = Output(Bool()) @@ -166,9 +165,9 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should NOT emit a Firrtl \"is invalid\" with overriden NotStrict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.NotStrict + import chisel3.ExplicitCompileOptions.NotStrict class ModuleWithoutDontCare extends Module { - override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true) + override val compileOptions = chisel3.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true) val io = IO(new TrivialInterface) io.out := io.in } @@ -177,8 +176,8 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should NOT emit a Firrtl \"is invalid\" with overriden NotStrict CompileOptions module definition") { - import chisel3.core.ExplicitCompileOptions.NotStrict - abstract class ExplicitInvalidateModule extends Module()(chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)) + import chisel3.ExplicitCompileOptions.NotStrict + abstract class ExplicitInvalidateModule extends Module()(chisel3.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)) class ModuleWithoutDontCare extends ExplicitInvalidateModule { val io = IO(new TrivialInterface) io.out := io.in @@ -188,9 +187,9 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should emit a Firrtl \"is invalid\" with overriden Strict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithoutDontCare extends Module { - override val compileOptions = chisel3.core.ExplicitCompileOptions.Strict.copy(explicitInvalidate = false) + override val compileOptions = chisel3.ExplicitCompileOptions.Strict.copy(explicitInvalidate = false) val io = IO(new TrivialInterface) io.out := io.in } @@ -199,8 +198,8 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should emit a Firrtl \"is invalid\" with overriden Strict CompileOptions module definition") { - import chisel3.core.ExplicitCompileOptions.Strict - abstract class ImplicitInvalidateModule extends Module()(chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = false)) + import chisel3.ExplicitCompileOptions.Strict + abstract class ImplicitInvalidateModule extends Module()(chisel3.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = false)) class ModuleWithoutDontCare extends ImplicitInvalidateModule { val io = IO(new TrivialInterface) io.out := io.in diff --git a/src/test/scala/chiselTests/LiteralExtractorSpec.scala b/src/test/scala/chiselTests/LiteralExtractorSpec.scala index c2d84831..533de888 100644 --- a/src/test/scala/chiselTests/LiteralExtractorSpec.scala +++ b/src/test/scala/chiselTests/LiteralExtractorSpec.scala @@ -3,11 +3,9 @@ package chiselTests import chisel3._ -import chisel3.core.FixedPoint -import chisel3.experimental.RawModule +import chisel3.experimental.{FixedPoint, RawModule} import chisel3.experimental.BundleLiterals._ import chisel3.testers.BasicTester -import org.scalatest._ class LiteralExtractorSpec extends ChiselFlatSpec { "litValue" should "return the literal value" in { @@ -70,15 +68,15 @@ class LiteralExtractorSpec extends ChiselFlatSpec { // the following errors with "assertion failed" println(outsideLiteral === insideLiteral) // scalastyle:ignore regex - // chisel3.core.assert(outsideLiteral === insideLiteral) + // chisel3.assert(outsideLiteral === insideLiteral) // the following lines of code error - // with "chisel3.core.BundleLitBinding cannot be cast to chisel3.core.ElementLitBinding" + // with "chisel3.internal.BundleLitBinding cannot be cast to chisel3.internal.ElementLitBinding" - chisel3.core.assert(outsideLiteral.x === insideLiteral.x) - chisel3.core.assert(outsideLiteral.y === insideLiteral.y) - chisel3.core.assert(outsideLiteral.x === 7.S) - chisel3.core.assert(outsideLiteral.y === 6.125.F(4.BP)) + chisel3.assert(outsideLiteral.x === insideLiteral.x) + chisel3.assert(outsideLiteral.y === insideLiteral.y) + chisel3.assert(outsideLiteral.x === 7.S) + chisel3.assert(outsideLiteral.y === 6.125.F(4.BP)) stop() } diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala index 93902d22..3264f4dd 100644 --- a/src/test/scala/chiselTests/MemorySearch.scala +++ b/src/test/scala/chiselTests/MemorySearch.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.testers.BasicTester class MemorySearch extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/MixedVecSpec.scala b/src/test/scala/chiselTests/MixedVecSpec.scala index 3bedf87f..5dd30270 100644 --- a/src/test/scala/chiselTests/MixedVecSpec.scala +++ b/src/test/scala/chiselTests/MixedVecSpec.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.core.Binding import chisel3.testers.BasicTester import chisel3.util._ import org.scalacheck.Shrink @@ -209,21 +208,21 @@ class MixedVecSpec extends ChiselPropSpec { } property("MixedVecs should not be able to take hardware types") { - a [Binding.ExpectedChiselTypeException] should be thrownBy { + a [ExpectedChiselTypeException] should be thrownBy { elaborate(new Module { val io = IO(new Bundle {}) val hw = Wire(MixedVec(Seq(UInt(8.W), Bool()))) val illegal = MixedVec(hw) }) } - a [Binding.ExpectedChiselTypeException] should be thrownBy { + a [ExpectedChiselTypeException] should be thrownBy { elaborate(new Module { val io = IO(new Bundle {}) val hw = Reg(MixedVec(Seq(UInt(8.W), Bool()))) val illegal = MixedVec(hw) }) } - a [Binding.ExpectedChiselTypeException] should be thrownBy { + a [ExpectedChiselTypeException] should be thrownBy { elaborate(new Module { val io = IO(new Bundle { val v = Input(MixedVec(Seq(UInt(8.W), Bool()))) diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 46e60064..ed624f0c 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -3,6 +3,7 @@ package chiselTests import chisel3._ +import chisel3.experimental.DataMirror class SimpleIO extends Bundle { val in = Input(UInt(32.W)) @@ -145,7 +146,7 @@ class ModuleSpec extends ChiselPropSpec { val a = IO(UInt(8.W)) val b = IO(Bool()) }) - assert(chisel3.experimental.DataMirror.modulePorts(m) == Seq( + assert(DataMirror.modulePorts(m) == Seq( "clock" -> m.clock, "reset" -> m.reset, "a" -> m.a, "b" -> m.b)) }) diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala index 38d010ee..e3501ad3 100644 --- a/src/test/scala/chiselTests/MulLookup.scala +++ b/src/test/scala/chiselTests/MulLookup.scala @@ -3,8 +3,6 @@ package chiselTests import chisel3._ -import org.scalatest._ -import org.scalatest.prop._ import chisel3.testers.BasicTester class MulLookup(val w: Int) extends Module { diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index 745e25de..8da5bc42 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -2,8 +2,6 @@ package chiselTests -import org.scalatest._ - import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ diff --git a/src/test/scala/chiselTests/NamingAnnotationTest.scala b/src/test/scala/chiselTests/NamingAnnotationTest.scala index aae9123e..82a5c109 100644 --- a/src/test/scala/chiselTests/NamingAnnotationTest.scala +++ b/src/test/scala/chiselTests/NamingAnnotationTest.scala @@ -3,11 +3,8 @@ package chiselTests import chisel3._ +import chisel3.experimental.{MultiIOModule, chiselName} import chisel3.internal.InstanceId -import chisel3.experimental.{chiselName, dump, MultiIOModule} -import org.scalatest._ -import org.scalatest.prop._ -import chisel3.testers.BasicTester import scala.collection.mutable.ListBuffer diff --git a/src/test/scala/chiselTests/OneHotMuxSpec.scala b/src/test/scala/chiselTests/OneHotMuxSpec.scala index be252bef..7476ebe2 100644 --- a/src/test/scala/chiselTests/OneHotMuxSpec.scala +++ b/src/test/scala/chiselTests/OneHotMuxSpec.scala @@ -2,9 +2,9 @@ package chiselTests -import Chisel.testers.BasicTester import chisel3._ import chisel3.experimental.FixedPoint +import chisel3.testers.BasicTester import chisel3.util.{Mux1H, UIntToOH} import org.scalatest._ diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala index 03b08385..b9b50baa 100644 --- a/src/test/scala/chiselTests/OptionBundle.scala +++ b/src/test/scala/chiselTests/OptionBundle.scala @@ -2,7 +2,6 @@ package chiselTests -import org.scalatest._ import chisel3._ import chisel3.testers.BasicTester diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala index 028b5baf..a04bf830 100644 --- a/src/test/scala/chiselTests/ParameterizedModule.scala +++ b/src/test/scala/chiselTests/ParameterizedModule.scala @@ -2,7 +2,6 @@ package chiselTests -import org.scalatest._ import chisel3._ import chisel3.testers.BasicTester diff --git a/src/test/scala/chiselTests/PopCount.scala b/src/test/scala/chiselTests/PopCount.scala index d9b3b837..1d6c86b9 100644 --- a/src/test/scala/chiselTests/PopCount.scala +++ b/src/test/scala/chiselTests/PopCount.scala @@ -4,8 +4,6 @@ package chiselTests import chisel3._ import chisel3.util.PopCount -import org.scalatest._ -import org.scalatest.prop._ import chisel3.testers.BasicTester class PopCountTester(n: Int) extends BasicTester { diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala index 7ba4bf5d..aeb92532 100644 --- a/src/test/scala/chiselTests/PrintableSpec.scala +++ b/src/test/scala/chiselTests/PrintableSpec.scala @@ -3,8 +3,6 @@ package chiselTests import org.scalatest.{FlatSpec, Matchers} -import scala.collection.mutable - import chisel3._ import chisel3.testers.BasicTester diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala index c1f084c6..3927ffa8 100644 --- a/src/test/scala/chiselTests/Printf.scala +++ b/src/test/scala/chiselTests/Printf.scala @@ -2,9 +2,7 @@ package chiselTests -import org.scalatest._ import chisel3._ -import chisel3.util._ import chisel3.testers.BasicTester class SinglePrintfTester() extends BasicTester { diff --git a/src/test/scala/chiselTests/QueueSpec.scala b/src/test/scala/chiselTests/QueueSpec.scala index 994f3e6d..c26e9485 100644 --- a/src/test/scala/chiselTests/QueueSpec.scala +++ b/src/test/scala/chiselTests/QueueSpec.scala @@ -2,8 +2,6 @@ package chiselTests -import org.scalatest._ -import org.scalatest.prop._ import org.scalacheck._ import chisel3._ diff --git a/src/test/scala/chiselTests/RebindingSpec.scala b/src/test/scala/chiselTests/RebindingSpec.scala index dddf26b6..f7a79ace 100644 --- a/src/test/scala/chiselTests/RebindingSpec.scala +++ b/src/test/scala/chiselTests/RebindingSpec.scala @@ -6,7 +6,7 @@ import chisel3._ class RebindingSpec extends ChiselFlatSpec { "Rebinding a literal" should "fail" in { - a [chisel3.core.Binding.BindingException] should be thrownBy { + a [BindingException] should be thrownBy { elaborate { new Module { val io = IO(new Bundle { val a = 4.U @@ -16,7 +16,7 @@ class RebindingSpec extends ChiselFlatSpec { } "Rebinding a hardware type" should "fail" in { - a [chisel3.core.Binding.BindingException] should be thrownBy { + a [BindingException] should be thrownBy { elaborate { new Module { val io = IO(new Bundle { val a = Reg(UInt(32.W)) diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index 7de85d04..c4df0742 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -2,12 +2,9 @@ package chiselTests -import firrtl.ir.Input -import org.scalatest._ -import org.scalatest.prop._ import chisel3._ import chisel3.util._ -import chisel3.core.DataMirror +import chisel3.experimental.DataMirror import chisel3.testers.BasicTester class RegSpec extends ChiselFlatSpec { diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 9f17c741..3c13273a 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -2,8 +2,6 @@ package chiselTests -import scala.collection.mutable.Stack - import chisel3._ import chisel3.util._ diff --git a/src/test/scala/chiselTests/Stop.scala b/src/test/scala/chiselTests/Stop.scala index 136fafc8..d912fe77 100644 --- a/src/test/scala/chiselTests/Stop.scala +++ b/src/test/scala/chiselTests/Stop.scala @@ -2,7 +2,6 @@ package chiselTests -import org.scalatest._ import chisel3._ import chisel3.testers.BasicTester diff --git a/src/test/scala/chiselTests/StrongEnum.scala b/src/test/scala/chiselTests/StrongEnum.scala index 6c87aee3..5e7ca2e1 100644 --- a/src/test/scala/chiselTests/StrongEnum.scala +++ b/src/test/scala/chiselTests/StrongEnum.scala @@ -245,7 +245,6 @@ class WidthTester extends BasicTester { } class StrongEnumFSMTester extends BasicTester { - import StrongEnumFSM.State import StrongEnumFSM.State._ val dut = Module(new StrongEnumFSM) diff --git a/src/test/scala/chiselTests/SwitchSpec.scala b/src/test/scala/chiselTests/SwitchSpec.scala index 81cf690a..2991a928 100644 --- a/src/test/scala/chiselTests/SwitchSpec.scala +++ b/src/test/scala/chiselTests/SwitchSpec.scala @@ -4,7 +4,6 @@ package chiselTests import chisel3._ import chisel3.util._ -import chisel3.testers.BasicTester class SwitchSpec extends ChiselFlatSpec { "switch" should "require literal conditions" in { diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index c09189e6..a0fda1ec 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -2,9 +2,6 @@ package chiselTests -import org.scalatest._ -import org.scalatest.prop._ - import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala index a7137699..7c571837 100644 --- a/src/test/scala/chiselTests/TesterDriverSpec.scala +++ b/src/test/scala/chiselTests/TesterDriverSpec.scala @@ -5,7 +5,6 @@ package chiselTests import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ -//import chisel3.core.ExplicitCompileOptions.Strict /** Extend BasicTester with a simple circuit and finish method. TesterDriver will call the * finish method after the FinishTester's constructor has completed, which will alter the diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index d8fde208..0884ad37 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -3,8 +3,6 @@ package chiselTests import chisel3._ -import chisel3.experimental.RawModule -import chisel3.core.Binding.BindingException import chisel3.testers.BasicTester import chisel3.util._ import org.scalacheck.Shrink diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala index 58d5a1bd..df9c8cce 100644 --- a/src/test/scala/chiselTests/When.scala +++ b/src/test/scala/chiselTests/When.scala @@ -2,8 +2,6 @@ package chiselTests -import org.scalatest._ - import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ diff --git a/src/test/scala/cookbook/RegOfVec.scala b/src/test/scala/cookbook/RegOfVec.scala index fee7f2e1..e5bb1ca8 100644 --- a/src/test/scala/cookbook/RegOfVec.scala +++ b/src/test/scala/cookbook/RegOfVec.scala @@ -7,7 +7,7 @@ import chisel3._ /* ### How do I create a Reg of type Vec? * * For information, please see the API documentation for Vec - * (https://chisel.eecs.berkeley.edu/api/index.html#chisel3.core.Vec) + * (https://chisel.eecs.berkeley.edu/api/index.html#chisel3.Vec) */ class RegOfVec extends CookbookTester(2) { // Reg of Vec of 32-bit UInts without initialization diff --git a/src/test/scala/cookbook/UInt2VecOfBool.scala b/src/test/scala/cookbook/UInt2VecOfBool.scala index 10250ad5..1f6d1006 100644 --- a/src/test/scala/cookbook/UInt2VecOfBool.scala +++ b/src/test/scala/cookbook/UInt2VecOfBool.scala @@ -6,7 +6,7 @@ import chisel3._ /* ### How do I create a Vec of Bools from a UInt? * - * Use the builtin function [[chisel3.core.Bits.asBools]] to create a Scala Seq of Bool, + * Use the builtin function [[chisel3.Bits.asBools]] to create a Scala Seq of Bool, * then wrap the resulting Seq in Vec(...) */ class UInt2VecOfBool extends CookbookTester(1) { |