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Diffstat (limited to 'src/test/scala/chiselTests/RebindingSpec.scala')
-rw-r--r--src/test/scala/chiselTests/RebindingSpec.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/RebindingSpec.scala b/src/test/scala/chiselTests/RebindingSpec.scala
index dddf26b6..f7a79ace 100644
--- a/src/test/scala/chiselTests/RebindingSpec.scala
+++ b/src/test/scala/chiselTests/RebindingSpec.scala
@@ -6,7 +6,7 @@ import chisel3._
class RebindingSpec extends ChiselFlatSpec {
"Rebinding a literal" should "fail" in {
- a [chisel3.core.Binding.BindingException] should be thrownBy {
+ a [BindingException] should be thrownBy {
elaborate { new Module {
val io = IO(new Bundle {
val a = 4.U
@@ -16,7 +16,7 @@ class RebindingSpec extends ChiselFlatSpec {
}
"Rebinding a hardware type" should "fail" in {
- a [chisel3.core.Binding.BindingException] should be thrownBy {
+ a [BindingException] should be thrownBy {
elaborate { new Module {
val io = IO(new Bundle {
val a = Reg(UInt(32.W))