diff options
Diffstat (limited to 'src')
74 files changed, 191 insertions, 791 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala index 9071491b..303f4599 100644 --- a/src/main/scala/chisel3/Driver.scala +++ b/src/main/scala/chisel3/Driver.scala @@ -3,18 +3,14 @@ package chisel3 import chisel3.internal.ErrorLog -import chisel3.internal.firrtl.Converter +import chisel3.internal.firrtl._ import chisel3.experimental.{RawModule, RunFirrtlTransform} import java.io._ -import net.jcazevedo.moultingyaml._ -import internal.firrtl._ import firrtl._ -import firrtl.annotations.{Annotation, JsonProtocol} -import firrtl.util.{ BackendCompilationUtilities => FirrtlBackendCompilationUtilities } - -import _root_.firrtl.annotations.AnnotationYamlProtocol._ +import firrtl.annotations.JsonProtocol +import firrtl.util.{BackendCompilationUtilities => FirrtlBackendCompilationUtilities} /** * The Driver provides methods to invoke the chisel3 compiler and the firrtl compiler. @@ -38,7 +34,6 @@ import _root_.firrtl.annotations.AnnotationYamlProtocol._ * chisel3.execute(args, () => new DUT) * }}} */ -import BuildInfo._ trait BackendCompilationUtilities extends FirrtlBackendCompilationUtilities { /** Compile Chirrtl to Verilog by invoking Firrtl inside the same JVM diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index ad49b095..6267bd62 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -3,6 +3,7 @@ /** The Chisel compatibility package allows legacy users to continue using the `Chisel` (capital C) package name * while moving to the more standard package naming convention `chisel3` (lowercase c). */ +import chisel3._ // required for implicit conversions. package object Chisel { // scalastyle:ignore package.object.name number.of.types number.of.methods import chisel3.internal.firrtl.Width @@ -12,28 +13,31 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t import scala.annotation.compileTimeOnly import scala.language.implicitConversions - implicit val defaultCompileOptions = chisel3.core.ExplicitCompileOptions.NotStrict + implicit val defaultCompileOptions = chisel3.ExplicitCompileOptions.NotStrict abstract class Direction case object INPUT extends Direction case object OUTPUT extends Direction case object NODIR extends Direction - val Input = chisel3.core.Input - val Output = chisel3.core.Output + val Input = chisel3.Input + val Output = chisel3.Output object Flipped { - def apply[T<:Data](target: T): T = chisel3.core.Flipped[T](target) + def apply[T<:Data](target: T): T = chisel3.Flipped[T](target) } implicit class AddDirectionToData[T<:Data](target: T) { - def asInput: T = chisel3.core.Input(target) - def asOutput: T = chisel3.core.Output(target) - def flip(): T = chisel3.core.Flipped(target) + def asInput: T = Input(target) + def asOutput: T = Output(target) + def flip(): T = Flipped(target) } implicit class AddDirMethodToData[T<:Data](target: T) { - import chisel3.core.{DataMirror, ActualDirection, requireIsHardware} + import chisel3.ActualDirection + import chisel3.experimental.DataMirror + import chisel3.internal.requireIsHardware + def dir: Direction = { requireIsHardware(target) // This has the side effect of calling _autoWrapPorts target match { @@ -47,7 +51,7 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t } } implicit class cloneTypeable[T <: Data](target: T) { - import chisel3.core.DataMirror + import chisel3.experimental.DataMirror def chiselCloneType: T = { DataMirror.internal.chiselTypeClone(target).asInstanceOf[T] } @@ -55,15 +59,15 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t type ChiselException = chisel3.internal.ChiselException - type Data = chisel3.core.Data - object Wire extends chisel3.core.WireFactory { - import chisel3.core.CompileOptions + type Data = chisel3.Data + object Wire extends WireFactory { + import chisel3.CompileOptions def apply[T <: Data](dummy: Int = 0, init: T)(implicit compileOptions: CompileOptions): T = - chisel3.core.WireDefault(init) + chisel3.WireDefault(init) def apply[T <: Data](t: T, init: T)(implicit compileOptions: CompileOptions): T = - chisel3.core.WireDefault(t, init) + chisel3.WireDefault(t, init) } object Clock { def apply(): Clock = new Clock @@ -71,17 +75,17 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t def apply(dir: Direction): Clock = { val result = apply() dir match { - case INPUT => chisel3.core.Input(result) - case OUTPUT => chisel3.core.Output(result) + case INPUT => Input(result) + case OUTPUT => Output(result) case _ => result } } } - type Clock = chisel3.core.Clock + type Clock = chisel3.Clock // Implicit conversion to allow fromBits because it's being deprecated in chisel3 implicit class fromBitsable[T <: Data](data: T) { - import chisel3.core.CompileOptions + import chisel3.CompileOptions import chisel3.internal.sourceinfo.SourceInfo /** Creates an new instance of this type, unpacking the input Bits into @@ -99,9 +103,9 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t } } - type Aggregate = chisel3.core.Aggregate - object Vec extends chisel3.core.VecFactory { - import chisel3.core.CompileOptions + type Aggregate = chisel3.Aggregate + object Vec extends chisel3.VecFactory { + import chisel3.CompileOptions import chisel3.internal.sourceinfo._ @deprecated("Vec argument order should be size, t; this will be removed by the official release", "chisel3") @@ -111,10 +115,10 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t /** Creates a new [[Vec]] of length `n` composed of the result of the given * function repeatedly applied. * - * @param n number of elements (and the number of times the function is - * called) + * @param n number of elements (and the number of times the function is + * called) * @param gen function that generates the [[Data]] that becomes the output - * element + * element */ def fill[T <: Data](n: Int)(gen: => T)(implicit compileOptions: CompileOptions): Vec[T] = apply(Seq.fill(n)(gen)) @@ -122,31 +126,31 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t def apply[T <: Data](elts: Seq[T]): Vec[T] = macro VecTransform.apply_elts /** @group SourceInfoTransformMacro */ def do_apply[T <: Data](elts: Seq[T])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = - chisel3.core.VecInit(elts) + chisel3.VecInit(elts) def apply[T <: Data](elt0: T, elts: T*): Vec[T] = macro VecTransform.apply_elt0 /** @group SourceInfoTransformMacro */ def do_apply[T <: Data](elt0: T, elts: T*) (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = - chisel3.core.VecInit(elt0 +: elts.toSeq) + chisel3.VecInit(elt0 +: elts.toSeq) def tabulate[T <: Data](n: Int)(gen: (Int) => T): Vec[T] = macro VecTransform.tabulate /** @group SourceInfoTransformMacro */ def do_tabulate[T <: Data](n: Int)(gen: (Int) => T) (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = - chisel3.core.VecInit.tabulate(n)(gen) + chisel3.VecInit.tabulate(n)(gen) } - type Vec[T <: Data] = chisel3.core.Vec[T] - type VecLike[T <: Data] = chisel3.core.VecLike[T] - type Record = chisel3.core.Record - type Bundle = chisel3.core.Bundle + type Vec[T <: Data] = chisel3.Vec[T] + type VecLike[T <: Data] = chisel3.VecLike[T] + type Record = chisel3.Record + type Bundle = chisel3.Bundle - val assert = chisel3.core.assert - val stop = chisel3.core.stop + val assert = chisel3.assert + val stop = chisel3.stop /** This contains literal constructor factory methods that are deprecated as of Chisel3. */ - trait UIntFactory extends chisel3.core.UIntFactory { + trait UIntFactory extends chisel3.UIntFactoryBase { /** Create a UInt literal with inferred width. */ def apply(n: String): UInt = n.asUInt /** Create a UInt literal with fixed width. */ @@ -171,8 +175,8 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t def apply(dir: Direction, width: Width): UInt = { val result = apply(width) dir match { - case INPUT => chisel3.core.Input(result) - case OUTPUT => chisel3.core.Output(result) + case INPUT => Input(result) + case OUTPUT => Output(result) case NODIR => result } } @@ -186,7 +190,7 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t /** This contains literal constructor factory methods that are deprecated as of Chisel3. */ - trait SIntFactory extends chisel3.core.SIntFactory { + trait SIntFactory extends chisel3.SIntFactoryBase { /** Create a SInt type or port with fixed width. */ def width(width: Int): SInt = apply(width.W) /** Create an SInt type with specified width. */ @@ -212,8 +216,8 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t def apply(dir: Direction, width: Width): SInt = { val result = apply(width) dir match { - case INPUT => chisel3.core.Input(result) - case OUTPUT => chisel3.core.Output(result) + case INPUT => Input(result) + case OUTPUT => Output(result) case NODIR => result } } @@ -221,7 +225,7 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t /** This contains literal constructor factory methods that are deprecated as of Chisel3. */ - trait BoolFactory extends chisel3.core.BoolFactory { + trait BoolFactory extends chisel3.BoolFactoryBase { /** Creates Bool literal. */ def apply(x: Boolean): Bool = x.B @@ -230,30 +234,30 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t def apply(dir: Direction): Bool = { val result = apply() dir match { - case INPUT => chisel3.core.Input(result) - case OUTPUT => chisel3.core.Output(result) + case INPUT => Input(result) + case OUTPUT => Output(result) case NODIR => result } } } - type Element = chisel3.core.Element - type Bits = chisel3.core.Bits + type Element = chisel3.Element + type Bits = chisel3.Bits object Bits extends UIntFactory - type Num[T <: Data] = chisel3.core.Num[T] - type UInt = chisel3.core.UInt + type Num[T <: Data] = chisel3.Num[T] + type UInt = chisel3.UInt object UInt extends UIntFactory - type SInt = chisel3.core.SInt + type SInt = chisel3.SInt object SInt extends SIntFactory - type Bool = chisel3.core.Bool + type Bool = chisel3.Bool object Bool extends BoolFactory - val Mux = chisel3.core.Mux - type Reset = chisel3.core.Reset + val Mux = chisel3.Mux + type Reset = chisel3.Reset implicit def resetToBool(reset: Reset): Bool = reset.asBool - import chisel3.core.Param - abstract class BlackBox(params: Map[String, Param] = Map.empty[String, Param]) extends chisel3.core.BlackBox(params) { + import chisel3.experimental.Param + abstract class BlackBox(params: Map[String, Param] = Map.empty[String, Param]) extends chisel3.BlackBox(params) { // This class auto-wraps the BlackBox with IO(...), allowing legacy code (where IO(...) wasn't // required) to build. override def _compatAutoWrapPorts(): Unit = { // scalastyle:ignore method.name @@ -262,15 +266,15 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t } } } - val Mem = chisel3.core.Mem - type MemBase[T <: Data] = chisel3.core.MemBase[T] - type Mem[T <: Data] = chisel3.core.Mem[T] - val SeqMem = chisel3.core.SyncReadMem - type SeqMem[T <: Data] = chisel3.core.SyncReadMem[T] + val Mem = chisel3.Mem + type MemBase[T <: Data] = chisel3.MemBase[T] + type Mem[T <: Data] = chisel3.Mem[T] + val SeqMem = chisel3.SyncReadMem + type SeqMem[T <: Data] = chisel3.SyncReadMem[T] - import chisel3.core.CompileOptions + import chisel3.CompileOptions abstract class CompatibilityModule(implicit moduleCompileOptions: CompileOptions) - extends chisel3.core.LegacyModule { + extends chisel3.experimental.LegacyModule { // This class auto-wraps the Module IO with IO(...), allowing legacy code (where IO(...) wasn't // required) to build. // Also provides the clock / reset constructors, which were used before withClock happened. @@ -296,22 +300,22 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t } } - val Module = chisel3.core.Module + val Module = chisel3.Module type Module = CompatibilityModule - val printf = chisel3.core.printf + val printf = chisel3.printf - val RegNext = chisel3.core.RegNext - val RegInit = chisel3.core.RegInit + val RegNext = chisel3.RegNext + val RegInit = chisel3.RegInit object Reg { - import chisel3.core.{Binding, CompileOptions} + import chisel3.CompileOptions import chisel3.internal.sourceinfo.SourceInfo - // Passthrough for chisel3.core.Reg + // Passthrough for chisel3.Reg // Single-element constructor to avoid issues caused by null default args in a type // parameterized scope. def apply[T <: Data](t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = - chisel3.core.Reg(t) + chisel3.Reg(t) /** Creates a register with optional next and initialization values. * @@ -332,7 +336,7 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t val reg = if (init ne null) { RegInit(t, init) } else { - chisel3.core.Reg(t) + chisel3.Reg(t) } if (next ne null) { reg := next @@ -352,15 +356,15 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t } } - val when = chisel3.core.when - type WhenContext = chisel3.core.WhenContext + val when = chisel3.when + type WhenContext = chisel3.WhenContext - implicit class fromBigIntToLiteral(x: BigInt) extends chisel3.core.fromBigIntToLiteral(x) - implicit class fromtIntToLiteral(x: Int) extends chisel3.core.fromIntToLiteral(x) - implicit class fromtLongToLiteral(x: Long) extends chisel3.core.fromLongToLiteral(x) - implicit class fromStringToLiteral(x: String) extends chisel3.core.fromStringToLiteral(x) - implicit class fromBooleanToLiteral(x: Boolean) extends chisel3.core.fromBooleanToLiteral(x) - implicit class fromIntToWidth(x: Int) extends chisel3.core.fromIntToWidth(x) + implicit class fromBigIntToLiteral(x: BigInt) extends chisel3.fromBigIntToLiteral(x) + implicit class fromtIntToLiteral(x: Int) extends chisel3.fromIntToLiteral(x) + implicit class fromtLongToLiteral(x: Long) extends chisel3.fromLongToLiteral(x) + implicit class fromStringToLiteral(x: String) extends chisel3.fromStringToLiteral(x) + implicit class fromBooleanToLiteral(x: Boolean) extends chisel3.fromBooleanToLiteral(x) + implicit class fromIntToWidth(x: Int) extends chisel3.fromIntToWidth(x) type BackendCompilationUtilities = firrtl.util.BackendCompilationUtilities val Driver = chisel3.Driver diff --git a/src/main/scala/chisel3/internal/firrtl/Converter.scala b/src/main/scala/chisel3/internal/firrtl/Converter.scala index 9366bea2..cdc55b59 100644 --- a/src/main/scala/chisel3/internal/firrtl/Converter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Converter.scala @@ -2,14 +2,13 @@ package chisel3.internal.firrtl import chisel3._ -import chisel3.core.{SpecifiedDirection, EnumType} import chisel3.experimental._ import chisel3.internal.sourceinfo.{NoSourceInfo, SourceLine, SourceInfo} import firrtl.{ir => fir} import chisel3.internal.{castToInt, throwException} import scala.annotation.tailrec -import scala.collection.immutable.{Queue} +import scala.collection.immutable.Queue private[chisel3] object Converter { // TODO modeled on unpack method on Printable, refactor? diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala index 050c8b72..2f1b75b0 100644 --- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -2,9 +2,8 @@ package chisel3.internal.firrtl import chisel3._ -import chisel3.core.{SpecifiedDirection, EnumType} import chisel3.experimental._ -import chisel3.internal.sourceinfo.{NoSourceInfo, SourceLine} +import chisel3.internal.BaseBlackBox private[chisel3] object Emitter { def emit(circuit: Circuit): String = new Emitter(circuit).toString @@ -28,7 +27,7 @@ private class Emitter(circuit: Circuit) { private def emitType(d: Data, clearDir: Boolean = false): String = d match { // scalastyle:ignore cyclomatic.complexity line.size.limit case d: Clock => "Clock" - case d: chisel3.core.EnumType => s"UInt${d.width}" + case d: EnumType => s"UInt${d.width}" case d: UInt => s"UInt${d.width}" case d: SInt => s"SInt${d.width}" case d: FixedPoint => s"Fixed${d.width}${d.binaryPoint}" @@ -110,8 +109,8 @@ private class Emitter(circuit: Circuit) { /** Generates the FIRRTL module declaration. */ private def moduleDecl(m: Component): String = m.id match { - case _: chisel3.core.BaseBlackBox => newline + s"extmodule ${m.name} : " - case _: chisel3.core.RawModule => newline + s"module ${m.name} : " + case _: BaseBlackBox => newline + s"extmodule ${m.name} : " + case _: RawModule => newline + s"module ${m.name} : " } /** Generates the FIRRTL module definition. diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala deleted file mode 100644 index 7587f211..00000000 --- a/src/main/scala/chisel3/package.scala +++ /dev/null @@ -1,523 +0,0 @@ -// See LICENSE for license details. - -import chisel3.core.CompileOptions - -/** The chisel3 package contains the chisel3 API. - * It maps core components into the public chisel3 namespace. - */ -package object chisel3 { // scalastyle:ignore package.object.name - import scala.language.implicitConversions - - import internal.firrtl.Width - - import util.BitPat - - import chisel3.util._ - import chisel3.internal.chiselRuntimeDeprecated - import chisel3.internal.firrtl.Port - import chisel3.core.CompileOptions - - val Input = chisel3.core.Input - val Output = chisel3.core.Output - val Flipped = chisel3.core.Flipped - val chiselTypeOf = chisel3.core.chiselTypeOf - - type Data = chisel3.core.Data - object Wire extends chisel3.core.WireFactory { - import chisel3.core.CompileOptions - - @chiselRuntimeDeprecated - @deprecated("Wire(init=init) is deprecated, use WireDefault(init) instead", "chisel3") - def apply[T <: Data](dummy: Int = 0, init: T)(implicit compileOptions: CompileOptions): T = - chisel3.core.WireDefault(init) - - @chiselRuntimeDeprecated - @deprecated("Wire(t, init) is deprecated, use WireDefault(t, init) instead", "chisel3") - def apply[T <: Data](t: T, init: T)(implicit compileOptions: CompileOptions): T = - chisel3.core.WireDefault(t, init) - - @chiselRuntimeDeprecated - @deprecated("Wire(t, init) is deprecated, use WireDefault(t, init) instead", "chisel3") - def apply[T <: Data](t: T, init: DontCare.type)(implicit compileOptions: CompileOptions): T = - chisel3.core.WireDefault(t, init) - } - val WireInit = chisel3.core.WireDefault - val WireDefault = chisel3.core.WireDefault - - val Clock = chisel3.core.Clock - type Clock = chisel3.core.Clock - - // Clock and reset scoping functions - val withClockAndReset = chisel3.core.withClockAndReset - val withClock = chisel3.core.withClock - val withReset = chisel3.core.withReset - - implicit class AddDirectionToData[T<:Data](target: T) { - @chiselRuntimeDeprecated - @deprecated("Input(Data) should be used over Data.asInput", "chisel3") - def asInput: T = Input(target) - - @chiselRuntimeDeprecated - @deprecated("Output(Data) should be used over Data.asOutput", "chisel3") - def asOutput: T = Output(target) - - @chiselRuntimeDeprecated - @deprecated("Flipped(Data) should be used over Data.flip", "chisel3") - def flip(): T = Flipped(target) - } - - implicit class fromBitsable[T <: Data](data: T) { - import chisel3.core.CompileOptions - import chisel3.internal.sourceinfo.SourceInfo - - @chiselRuntimeDeprecated - @deprecated("fromBits is deprecated, use asTypeOf instead", "chisel3") - def fromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { - that.asTypeOf(data) - } - } - - implicit class cloneTypeable[T <: Data](target: T) { - @chiselRuntimeDeprecated - @deprecated("chiselCloneType is deprecated, use chiselTypeOf(...) to get the Chisel Type of a hardware object", "chisel3") // scalastyle:ignore line.size.limit - def chiselCloneType: T = { - target.cloneTypeFull.asInstanceOf[T] - } - } - - type Aggregate = chisel3.core.Aggregate - object Vec extends chisel3.core.VecFactory { - import scala.language.experimental.macros - import chisel3.core.CompileOptions - import chisel3.internal.sourceinfo._ - - @chiselRuntimeDeprecated - @deprecated("Vec argument order should be size, t; this will be removed by the official release", "chisel3") - def apply[T <: Data](gen: T, n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = - apply(n, gen) - - @chiselRuntimeDeprecated - @deprecated("Vec.fill(n)(gen) is deprecated, use VecInit(Seq.fill(n)(gen)) instead", "chisel3") - def fill[T <: Data](n: Int)(gen: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = - apply(Seq.fill(n)(gen)) - - def apply[T <: Data](elts: Seq[T]): Vec[T] = macro VecTransform.apply_elts - @chiselRuntimeDeprecated - @deprecated("Vec(elts) is deprecated, use VecInit(elts) instead", "chisel3") - def do_apply[T <: Data](elts: Seq[T])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = - chisel3.core.VecInit(elts) - - def apply[T <: Data](elt0: T, elts: T*): Vec[T] = macro VecTransform.apply_elt0 - @chiselRuntimeDeprecated - @deprecated("Vec(elt0, ...) is deprecated, use VecInit(elt0, ...) instead", "chisel3") - def do_apply[T <: Data](elt0: T, elts: T*) - (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = - chisel3.core.VecInit(elt0 +: elts.toSeq) - - def tabulate[T <: Data](n: Int)(gen: (Int) => T): Vec[T] = macro VecTransform.tabulate - @chiselRuntimeDeprecated - @deprecated("Vec.tabulate(n)(gen) is deprecated, use VecInit.tabulate(n)(gen) instead", "chisel3") - def do_tabulate[T <: Data](n: Int)(gen: (Int) => T) - (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = - chisel3.core.VecInit.tabulate(n)(gen) - } - val VecInit = chisel3.core.VecInit - type Vec[T <: Data] = chisel3.core.Vec[T] - type VecLike[T <: Data] = chisel3.core.VecLike[T] - type Bundle = chisel3.core.Bundle - type IgnoreSeqInBundle = chisel3.core.IgnoreSeqInBundle - type Record = chisel3.core.Record - - val assert = chisel3.core.assert - - type Element = chisel3.core.Element - type Bits = chisel3.core.Bits - - // Some possible regex replacements for the literal specifier deprecation: - // (note: these are not guaranteed to handle all edge cases! check all replacements!) - // Bool\((true|false)\) - // => $1.B - // UInt\(width\s*=\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) - // => UInt($1.W) - // (UInt|SInt|Bits).width\((\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) - // => $1($2.W) - // (U|S)Int\((-?\d+|0[xX][0-9a-fA-F]+)\) - // => $2.$1 - // UInt\((\d+|0[xX][0-9a-fA-F]+),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) - // => $1.U($2.W) - // (UInt|SInt|Bool)\(([_a-zA-Z][_0-9a-zA-Z]*)\) - // => $2.as$1 - // (UInt|SInt)\(([_a-zA-Z][_0-9a-zA-Z]*),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) - // => $2.as$1($3.W) - - /** This contains literal constructor factory methods that are deprecated as of Chisel3. - * These will be removed very soon. It's recommended you port your code ASAP. - */ - trait UIntFactory extends chisel3.core.UIntFactory { - /** Create a UInt literal with inferred width. */ - @chiselRuntimeDeprecated - @deprecated("use n.U", "chisel3, will be removed by end of 2017") - def apply(n: String): UInt = n.asUInt - - /** Create a UInt literal with fixed width. */ - @chiselRuntimeDeprecated - @deprecated("use n.U(width.W)", "chisel3, will be removed by end of 2017") - def apply(n: String, width: Int): UInt = n.asUInt(width.W) - - /** Create a UInt literal with specified width. */ - @chiselRuntimeDeprecated - @deprecated("use value.U(width)", "chisel3, will be removed by end of 2017") - def apply(value: BigInt, width: Width): UInt = value.asUInt(width) - - /** Create a UInt literal with fixed width. */ - @chiselRuntimeDeprecated - @deprecated("use value.U(width.W)", "chisel3, will be removed by end of 2017") - def apply(value: BigInt, width: Int): UInt = value.asUInt(width.W) - - /** Create a UInt literal with inferred width.- compatibility with Chisel2. */ - @chiselRuntimeDeprecated - @deprecated("use value.U", "chisel3, will be removed by end of 2017") - def apply(value: BigInt): UInt = value.asUInt - - /** Create a UInt with a specified width */ - @chiselRuntimeDeprecated - @deprecated("use UInt(width.W)", "chisel3, will be removed by end of 2017") - def width(width: Int): UInt = apply(width.W) - - /** Create a UInt port with specified width. */ - @chiselRuntimeDeprecated - @deprecated("use UInt(width)", "chisel3, will be removed by end of 2017") - def width(width: Width): UInt = apply(width) - } - - /** This contains literal constructor factory methods that are deprecated as of Chisel3. - * These will be removed very soon. It's recommended you move your code soon. - */ - trait SIntFactory extends chisel3.core.SIntFactory { - /** Create a SInt type or port with fixed width. */ - @chiselRuntimeDeprecated - @deprecated("use SInt(width.W)", "chisel3, will be removed by end of 2017") - def width(width: Int): SInt = apply(width.W) - - /** Create an SInt type with specified width. */ - @chiselRuntimeDeprecated - @deprecated("use SInt(width)", "chisel3, will be removed by end of 2017") - def width(width: Width): SInt = apply(width) - - /** Create an SInt literal with inferred width. */ - @chiselRuntimeDeprecated - @deprecated("use value.S", "chisel3, will be removed by end of 2017") - def apply(value: BigInt): SInt = value.asSInt - - /** Create an SInt literal with fixed width. */ - @chiselRuntimeDeprecated - @deprecated("use value.S(width.W)", "chisel3, will be removed by end of 2017") - def apply(value: BigInt, width: Int): SInt = value.asSInt(width.W) - - /** Create an SInt literal with specified width. */ - @chiselRuntimeDeprecated - @deprecated("use value.S(width)", "chisel3, will be removed by end of 2017") - def apply(value: BigInt, width: Width): SInt = value.asSInt(width) - - @chiselRuntimeDeprecated - @deprecated("use value.S", "chisel3, will be removed by end of 2017") - def Lit(value: BigInt): SInt = value.asSInt // scalastyle:ignore method.name - - @chiselRuntimeDeprecated - @deprecated("use value.S(width)", "chisel3, will be removed by end of 2017") - def Lit(value: BigInt, width: Int): SInt = value.asSInt(width.W) // scalastyle:ignore method.name - } - - /** This contains literal constructor factory methods that are deprecated as of Chisel3. - * These will be removed very soon. It's recommended you move your code soon. - */ - trait BoolFactory extends chisel3.core.BoolFactory { - /** Creates Bool literal. - */ - @chiselRuntimeDeprecated - @deprecated("use x.B", "chisel3, will be removed by end of 2017") - def apply(x: Boolean): Bool = x.B - } - - object Bits extends UIntFactory - type Num[T <: Data] = chisel3.core.Num[T] - type UInt = chisel3.core.UInt - object UInt extends UIntFactory - type SInt = chisel3.core.SInt - object SInt extends SIntFactory - type Bool = chisel3.core.Bool - object Bool extends BoolFactory - val Mux = chisel3.core.Mux - - type BlackBox = chisel3.core.BlackBox - - type InstanceId = chisel3.internal.InstanceId - - val Mem = chisel3.core.Mem - type MemBase[T <: Data] = chisel3.core.MemBase[T] - type Mem[T <: Data] = chisel3.core.Mem[T] - val SyncReadMem = chisel3.core.SyncReadMem - type SyncReadMem[T <: Data] = chisel3.core.SyncReadMem[T] - - @deprecated("Use 'SyncReadMem'", "chisel3") - val SeqMem = chisel3.core.SyncReadMem - @deprecated("Use 'SyncReadMem'", "chisel3") - type SeqMem[T <: Data] = chisel3.core.SyncReadMem[T] - - val Module = chisel3.core.Module - type Module = chisel3.core.LegacyModule - - val printf = chisel3.core.printf - - val RegNext = chisel3.core.RegNext - val RegInit = chisel3.core.RegInit - object Reg { - import chisel3.core.{Binding, CompileOptions} - import chisel3.internal.sourceinfo.SourceInfo - import chisel3.internal.throwException - - // Passthrough for chisel3.core.Reg - // TODO: make val Reg = chisel3.core.Reg once we eliminate the legacy Reg constructor - def apply[T <: Data](t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = - chisel3.core.Reg(t) - - @chiselRuntimeDeprecated - @deprecated("Use Reg(t), RegNext(next, [init]) or RegInit([t], init) instead", "chisel3") - def apply[T <: Data](t: T = null, next: T = null, init: T = null) - (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { - if (t ne null) { - val reg = if (init ne null) { - RegInit(t, init) - } else { - chisel3.core.Reg(t) - } - if (next ne null) { - reg := next - } - reg - } else if (next ne null) { - if (init ne null) { - RegNext(next, init) - } else { - RegNext(next) - } - } else if (init ne null) { - RegInit(init) - } else { - throwException("cannot infer type") - } - } - } - - val when = chisel3.core.when - type WhenContext = chisel3.core.WhenContext - - type Printable = chisel3.core.Printable - val Printable = chisel3.core.Printable - type Printables = chisel3.core.Printables - val Printables = chisel3.core.Printables - type PString = chisel3.core.PString - val PString = chisel3.core.PString - type FirrtlFormat = chisel3.core.FirrtlFormat - val FirrtlFormat = chisel3.core.FirrtlFormat - type Decimal = chisel3.core.Decimal - val Decimal = chisel3.core.Decimal - type Hexadecimal = chisel3.core.Hexadecimal - val Hexadecimal = chisel3.core.Hexadecimal - type Binary = chisel3.core.Binary - val Binary = chisel3.core.Binary - type Character = chisel3.core.Character - val Character = chisel3.core.Character - type Name = chisel3.core.Name - val Name = chisel3.core.Name - type FullName = chisel3.core.FullName - val FullName = chisel3.core.FullName - val Percent = chisel3.core.Percent - - /** Implicit for custom Printable string interpolator */ - implicit class PrintableHelper(val sc: StringContext) extends AnyVal { - /** Custom string interpolator for generating Printables: p"..." - * Will call .toString on any non-Printable arguments (mimicking s"...") - */ - def p(args: Any*): Printable = { - sc.checkLengths(args) // Enforce sc.parts.size == pargs.size + 1 - val pargs: Seq[Option[Printable]] = args map { - case p: Printable => Some(p) - case d: Data => Some(d.toPrintable) - case any => for { - v <- Option(any) // Handle null inputs - str = v.toString - if !str.isEmpty // Handle empty Strings - } yield PString(str) - } - val parts = sc.parts map StringContext.treatEscapes - // Zip sc.parts and pargs together ito flat Seq - // eg. Seq(sc.parts(0), pargs(0), sc.parts(1), pargs(1), ...) - val seq = for { // append None because sc.parts.size == pargs.size + 1 - (literal, arg) <- parts zip (pargs :+ None) - optPable <- Seq(Some(PString(literal)), arg) - pable <- optPable // Remove Option[_] - } yield pable - Printables(seq) - } - } - - implicit def string2Printable(str: String): Printable = PString(str) - - implicit class fromBigIntToLiteral(x: BigInt) extends chisel3.core.fromBigIntToLiteral(x) - implicit class fromtIntToLiteral(x: Int) extends chisel3.core.fromIntToLiteral(x) - implicit class fromtLongToLiteral(x: Long) extends chisel3.core.fromLongToLiteral(x) - implicit class fromStringToLiteral(x: String) extends chisel3.core.fromStringToLiteral(x) - implicit class fromBooleanToLiteral(x: Boolean) extends chisel3.core.fromBooleanToLiteral(x) - implicit class fromDoubleToLiteral(x: Double) extends chisel3.core.fromDoubleToLiteral(x) - implicit class fromIntToWidth(x: Int) extends chisel3.core.fromIntToWidth(x) - implicit class fromIntToBinaryPoint(x: Int) extends chisel3.core.fromIntToBinaryPoint(x) - - implicit class fromUIntToBitPatComparable(x: UInt) extends chisel3.SourceInfoDoc { - import scala.language.experimental.macros - import internal.sourceinfo.{SourceInfo, SourceInfoTransform} - - final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg - final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg - - /** @group SourceInfoTransformMacro */ - def do_=== (that: BitPat) // scalastyle:ignore method.name - (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that === x - /** @group SourceInfoTransformMacro */ - def do_=/= (that: BitPat) // scalastyle:ignore method.name - (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that =/= x - - final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg - @chiselRuntimeDeprecated - @deprecated("Use '=/=', which avoids potential precedence problems", "chisel3") - def do_!= (that: BitPat) // scalastyle:ignore method.name - (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that != x - } - - - type ChiselException = chisel3.internal.ChiselException - - // Debugger/Tester access to internal Chisel data structures and methods. - def getDataElements(a: Aggregate): Seq[Element] = { - a.allElements - } - def getModulePorts(m: Module): Seq[Port] = m.getPorts - // Invalidate API - a DontCare element for explicit assignment to outputs, - // indicating the signal is intentionally not driven. - val DontCare = chisel3.core.DontCare - - /** Package for experimental features, which may have their API changed, be removed, etc. - * - * Because its contents won't necessarily have the same level of stability and support as - * non-experimental, you must explicitly import this package to use its contents. - */ - object experimental { // scalastyle:ignore object.name - type Param = chisel3.core.Param - type IntParam = chisel3.core.IntParam - val IntParam = chisel3.core.IntParam - type DoubleParam = chisel3.core.DoubleParam - val DoubleParam = chisel3.core.DoubleParam - type StringParam = chisel3.core.StringParam - val StringParam = chisel3.core.StringParam - type RawParam = chisel3.core.RawParam - val RawParam = chisel3.core.RawParam - - type Analog = chisel3.core.Analog - val Analog = chisel3.core.Analog - val attach = chisel3.core.attach - - type ChiselEnum = chisel3.core.EnumFactory - val EnumAnnotations = chisel3.core.EnumAnnotations - - @deprecated("Use the version in chisel3._", "chisel3.2") - val withClockAndReset = chisel3.core.withClockAndReset - @deprecated("Use the version in chisel3._", "chisel3.2") - val withClock = chisel3.core.withClock - @deprecated("Use the version in chisel3._", "chisel3.2") - val withReset = chisel3.core.withReset - - val dontTouch = chisel3.core.dontTouch - val doNotDedup = chisel3.core.doNotDedup - - type BaseModule = chisel3.core.BaseModule - type RawModule = chisel3.core.RawModule - type MultiIOModule = chisel3.core.MultiIOModule - type ExtModule = chisel3.core.ExtModule - - val IO = chisel3.core.IO - - // Rocket Chip-style clonemodule - - /** A record containing the results of CloneModuleAsRecord - * The apply method is retrieves the element with the supplied name. - */ - type ClonePorts = chisel3.core.BaseModule.ClonePorts - - object CloneModuleAsRecord { - /** Clones an existing module and returns a record of all its top-level ports. - * Each element of the record is named with a string matching the - * corresponding port's name and shares the port's type. - * @example {{{ - * val q1 = Module(new Queue(UInt(32.W), 2)) - * val q2_io = CloneModuleAsRecord(q1)("io").asInstanceOf[q1.io.type] - * q2_io.enq <> q1.io.deq - * }}} - */ - def apply(proto: BaseModule)(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: chisel3.core.CompileOptions): ClonePorts = { // scalastyle:ignore line.size.limit - chisel3.core.BaseModule.cloneIORecord(proto) - } - } - - // Implicit conversions for BlackBox Parameters - implicit def fromIntToIntParam(x: Int): IntParam = IntParam(BigInt(x)) - implicit def fromLongToIntParam(x: Long): IntParam = IntParam(BigInt(x)) - implicit def fromBigIntToIntParam(x: BigInt): IntParam = IntParam(x) - implicit def fromDoubleToDoubleParam(x: Double): DoubleParam = DoubleParam(x) - implicit def fromStringToStringParam(x: String): StringParam = StringParam(x) - - // Fixed Point is experimental for now - type FixedPoint = chisel3.core.FixedPoint - val FixedPoint = chisel3.core.FixedPoint - - type ChiselAnnotation = chisel3.core.ChiselAnnotation - val ChiselAnnotation = chisel3.core.ChiselAnnotation - type RunFirrtlTransform = chisel3.core.RunFirrtlTransform - - val annotate = chisel3.core.annotate - - val DataMirror = chisel3.core.DataMirror - val requireIsHardware = chisel3.core.requireIsHardware - val requireIsChiselType = chisel3.core.requireIsChiselType - type Direction = chisel3.core.ActualDirection - val Direction = chisel3.core.ActualDirection - - implicit class ChiselRange(val sc: StringContext) extends AnyVal { - import scala.language.experimental.macros - import internal.firrtl.NumericBound - - /** Specifies a range using mathematical range notation. Variables can be interpolated using - * standard string interpolation syntax. - * @example {{{ - * UInt(range"[0, 2)") - * UInt(range"[0, \$myInt)") - * UInt(range"[0, \${myInt + 2})") - * }}} - */ - def range(args: Any*): (NumericBound[Int], NumericBound[Int]) = macro chisel3.internal.RangeTransform.apply - } - - import scala.annotation.compileTimeOnly - - class dump extends chisel3.internal.naming.dump // scalastyle:ignore class.name - class treedump extends chisel3.internal.naming.treedump // scalastyle:ignore class.name - class chiselName extends chisel3.internal.naming.chiselName // scalastyle:ignore class.name - - object BundleLiterals { - implicit class AddBundleLiteralConstructor[T <: Bundle](x: T) { - def Lit(elems: (T => (Data, Data))*): T = { - x._makeLit(elems: _*) - } - } - } - } -} diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala index c21a2cdd..47dbda85 100644 --- a/src/main/scala/chisel3/testers/BasicTester.scala +++ b/src/main/scala/chisel3/testers/BasicTester.scala @@ -5,11 +5,9 @@ import chisel3._ import scala.language.experimental.macros -import internal._ -import internal.Builder.pushCommand -import internal.firrtl._ -import internal.sourceinfo.SourceInfo -//import chisel3.core.ExplicitCompileOptions.NotStrict +import chisel3.internal.Builder.pushCommand +import chisel3.internal.firrtl._ +import chisel3.internal.sourceinfo.SourceInfo class BasicTester extends Module() { // The testbench has no IOs, rather it should communicate using printf, assert, and stop. diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala index 6cba497e..b8a239d0 100644 --- a/src/main/scala/chisel3/util/BitPat.scala +++ b/src/main/scala/chisel3/util/BitPat.scala @@ -4,10 +4,10 @@ package chisel3.util import scala.language.experimental.macros import chisel3._ -import chisel3.core.CompileOptions import chisel3.internal.chiselRuntimeDeprecated import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform} + object BitPat { /** Parses a bit pattern string into (bits, mask, width). * @@ -77,6 +77,28 @@ object BitPat { val len = if (x.isWidthKnown) x.getWidth else 0 apply("b" + x.litValue.toString(2).reverse.padTo(len, "0").reverse.mkString) } + + implicit class fromUIntToBitPatComparable(x: UInt) extends SourceInfoDoc { + import internal.sourceinfo.{SourceInfo, SourceInfoTransform} + + import scala.language.experimental.macros + + final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg + final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg + + /** @group SourceInfoTransformMacro */ + def do_=== (that: BitPat) // scalastyle:ignore method.name + (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that === x + /** @group SourceInfoTransformMacro */ + def do_=/= (that: BitPat) // scalastyle:ignore method.name + (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that =/= x + + final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg + @chiselRuntimeDeprecated + @deprecated("Use '=/=', which avoids potential precedence problems", "chisel3") + def do_!= (that: BitPat) // scalastyle:ignore method.name + (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that != x + } } /** Bit patterns are literals with masks, used to represent values with don't diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala index 1692e083..bbed5f07 100644 --- a/src/main/scala/chisel3/util/Bitwise.scala +++ b/src/main/scala/chisel3/util/Bitwise.scala @@ -6,7 +6,6 @@ package chisel3.util import chisel3._ -import chisel3.core.SeqUtils /** Creates repetitions of each bit of the input in order. * diff --git a/src/main/scala/chisel3/util/Cat.scala b/src/main/scala/chisel3/util/Cat.scala index 78801541..ee01c6e6 100644 --- a/src/main/scala/chisel3/util/Cat.scala +++ b/src/main/scala/chisel3/util/Cat.scala @@ -3,7 +3,6 @@ package chisel3.util import chisel3._ -import chisel3.core.SeqUtils /** Concatenates elements of the input, in order, together. * diff --git a/src/main/scala/chisel3/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala index 3630f8ad..c87c2cb6 100644 --- a/src/main/scala/chisel3/util/Conditional.scala +++ b/src/main/scala/chisel3/util/Conditional.scala @@ -7,7 +7,6 @@ package chisel3.util import scala.language.reflectiveCalls import scala.language.experimental.macros -import scala.reflect.runtime.universe._ import scala.reflect.macros.blackbox._ import chisel3._ diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 7ab13922..047973f5 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -6,7 +6,7 @@ package chisel3.util import chisel3._ -import chisel3.experimental.{DataMirror, Direction, requireIsChiselType} +import chisel3.experimental.{DataMirror, Direction, MultiIOModule, requireIsChiselType} import chisel3.internal.naming._ // can't use chisel3_ version because of compile order /** An I/O Bundle containing 'valid' and 'ready' signals that handshake @@ -21,7 +21,7 @@ abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle { // Compatibility hack for rocket-chip private val genType = (DataMirror.internal.isSynthesizable(gen), chisel3.internal.Builder.currentModule) match { - case (true, Some(module: chisel3.core.MultiIOModule)) + case (true, Some(module: MultiIOModule)) if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen) case _ => gen } @@ -186,7 +186,7 @@ class Queue[T <: Data](gen: T, val entries: Int, pipe: Boolean = false, flow: Boolean = false) - (implicit compileOptions: chisel3.core.CompileOptions) + (implicit compileOptions: chisel3.CompileOptions) extends Module() { @deprecated("Module constructor with override _reset deprecated, use withReset", "chisel3") def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, override_reset: Option[Bool]) = { diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala index 24ea0470..4c89acdd 100644 --- a/src/main/scala/chisel3/util/ImplicitConversions.scala +++ b/src/main/scala/chisel3/util/ImplicitConversions.scala @@ -12,6 +12,6 @@ import scala.language.implicitConversions object ImplicitConversions { // The explicit fromIntToLiteral resolves an ambiguous conversion between fromIntToLiteral and // UInt.asUInt. - implicit def intToUInt(x: Int): UInt = chisel3.core.fromIntToLiteral(x).asUInt + implicit def intToUInt(x: Int): UInt = chisel3.fromIntToLiteral(x).asUInt implicit def booleanToBool(x: Boolean): Bool = x.B } diff --git a/src/main/scala/chisel3/util/MixedVec.scala b/src/main/scala/chisel3/util/MixedVec.scala index 9b70cd41..70b0656f 100644 --- a/src/main/scala/chisel3/util/MixedVec.scala +++ b/src/main/scala/chisel3/util/MixedVec.scala @@ -3,7 +3,7 @@ package chisel3.util import chisel3._ -import chisel3.core.{Data, requireIsChiselType, requireIsHardware} +import chisel3.internal.requireIsChiselType import scala.collection.immutable.ListMap @@ -11,7 +11,7 @@ import scala.collection.immutable.ListMap * Create a MixedVec wire with default values as specified, and type of each element inferred from * those default values. * - * This is analogous to [[chisel3.core.VecInit]]. + * This is analogous to [[VecInit]]. * @return MixedVec with given values assigned * * @example {{{ diff --git a/src/main/scala/chisel3/util/Mux.scala b/src/main/scala/chisel3/util/Mux.scala index 1fa7518e..342531bd 100644 --- a/src/main/scala/chisel3/util/Mux.scala +++ b/src/main/scala/chisel3/util/Mux.scala @@ -6,7 +6,6 @@ package chisel3.util import chisel3._ -import chisel3.core.SeqUtils /** Builds a Mux tree out of the input signal vector using a one hot encoded * select signal. Returns the output of the Mux tree. diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index c6458b9d..ef27263e 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -6,8 +6,6 @@ package chisel3.util import chisel3._ -import chisel3.core.CompileOptions -import chisel3.experimental.DataMirror /** A [[Bundle]] that adds a `valid` bit to some data. This indicates that the user expects a "valid" interface between * a producer and a consumer. Here, the producer asserts the `valid` bit when data on the `bits` line contains valid diff --git a/src/main/scala/chisel3/util/experimental/BoringUtils.scala b/src/main/scala/chisel3/util/experimental/BoringUtils.scala index a6f2d52a..da5b3fd0 100644 --- a/src/main/scala/chisel3/util/experimental/BoringUtils.scala +++ b/src/main/scala/chisel3/util/experimental/BoringUtils.scala @@ -4,13 +4,12 @@ package chisel3.util.experimental import chisel3._ import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform, annotate} -import chisel3.internal.{InstanceId, NamedComponent} +import chisel3.internal.{InstanceId, NamedComponent, Namespace} import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation} import firrtl.passes.wiring.{WiringTransform, SourceAnnotation, SinkAnnotation} import firrtl.annotations.{ModuleName, ComponentName} import scala.concurrent.SyncVar -import chisel3.internal.Namespace /** An exception related to BoringUtils * @param message the exception message diff --git a/src/main/scala/chisel3/util/experimental/Inline.scala b/src/main/scala/chisel3/util/experimental/Inline.scala index 753c36af..7e8a35fb 100644 --- a/src/main/scala/chisel3/util/experimental/Inline.scala +++ b/src/main/scala/chisel3/util/experimental/Inline.scala @@ -3,12 +3,11 @@ package chisel3.util.experimental import chisel3._ -import chisel3.internal.InstanceId import chisel3.experimental.{BaseModule, ChiselAnnotation, RunFirrtlTransform} import firrtl.Transform import firrtl.passes.{InlineAnnotation, InlineInstances} import firrtl.transforms.{NoDedupAnnotation, FlattenAnnotation, Flatten} -import firrtl.annotations.{CircuitName, ModuleName, ComponentName, Annotation} +import firrtl.annotations.Annotation /** Inlines an instance of a module * diff --git a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala index 2d23de38..3d14b5c2 100644 --- a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala +++ b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala @@ -3,10 +3,8 @@ package chisel3.util.experimental import chisel3._ -import chisel3.experimental.annotate -// import chisel3.InstanceId -import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform} -import firrtl.annotations.{MemoryLoadFileType, _} +import chisel3.experimental.{RunFirrtlTransform, annotate, ChiselAnnotation} +import firrtl.annotations._ import firrtl.ir.{Module => _, _} import firrtl.transforms.BlackBoxInlineAnno import firrtl.Mappers._ diff --git a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala index 853d82af..b8a0a5ef 100644 --- a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala +++ b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala @@ -3,12 +3,11 @@ package chiselTests import chisel3._ -import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform} +import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform, annotate} import chisel3.internal.InstanceId import chisel3.testers.BasicTester import firrtl.{CircuitForm, CircuitState, LowForm, Transform} import firrtl.annotations.{ - Annotation, SingleTargetAnnotation, ModuleName, Named diff --git a/src/test/scala/chiselTests/AnnotationNoDedup.scala b/src/test/scala/chiselTests/AnnotationNoDedup.scala index d94cc2fc..3cb457eb 100644 --- a/src/test/scala/chiselTests/AnnotationNoDedup.scala +++ b/src/test/scala/chiselTests/AnnotationNoDedup.scala @@ -3,9 +3,8 @@ package chiselTests import chisel3._ -import chisel3.experimental.{annotate, ChiselAnnotation, doNotDedup} +import chisel3.experimental.doNotDedup import firrtl.FirrtlExecutionSuccess -import firrtl.transforms.NoDedupAnnotation import org.scalatest.{FreeSpec, Matchers} diff --git a/src/test/scala/chiselTests/AsTypeOfTester.scala b/src/test/scala/chiselTests/AsTypeOfTester.scala index 563e2b11..7861f51b 100644 --- a/src/test/scala/chiselTests/AsTypeOfTester.scala +++ b/src/test/scala/chiselTests/AsTypeOfTester.scala @@ -2,12 +2,9 @@ package chiselTests -import org.scalatest._ - import chisel3._ import chisel3.experimental.{DataMirror, FixedPoint, ChiselEnum} import chisel3.testers.BasicTester -import chisel3.util._ class AsTypeOfBundleTester extends BasicTester { class MultiTypeBundle extends Bundle { diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala index fab6f87b..3bea2e4f 100644 --- a/src/test/scala/chiselTests/Assert.scala +++ b/src/test/scala/chiselTests/Assert.scala @@ -2,7 +2,6 @@ package chiselTests -import org.scalatest._ import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ diff --git a/src/test/scala/chiselTests/AutoClonetypeSpec.scala b/src/test/scala/chiselTests/AutoClonetypeSpec.scala index e533eb94..7ab20e5a 100644 --- a/src/test/scala/chiselTests/AutoClonetypeSpec.scala +++ b/src/test/scala/chiselTests/AutoClonetypeSpec.scala @@ -4,8 +4,6 @@ package chiselTests import chisel3._ -import chisel3.testers.BasicTester - class BundleWithIntArg(val i: Int) extends Bundle { val out = UInt(i.W) } diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala index 1b91da3c..0ac28899 100644 --- a/src/test/scala/chiselTests/BetterNamingTests.scala +++ b/src/test/scala/chiselTests/BetterNamingTests.scala @@ -2,11 +2,11 @@ package chiselTests -import collection.mutable - import chisel3._ import chisel3.util._ +import scala.collection.mutable + // Defined outside of the class so we don't get $ in name class Other(w: Int) extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala index 1292222c..505178a4 100644 --- a/src/test/scala/chiselTests/BitwiseOps.scala +++ b/src/test/scala/chiselTests/BitwiseOps.scala @@ -3,8 +3,6 @@ package chiselTests import chisel3._ -import org.scalatest._ -import org.scalatest.prop._ import chisel3.testers.BasicTester class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester { diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala index b45171f4..70ddd4da 100644 --- a/src/test/scala/chiselTests/BlackBox.scala +++ b/src/test/scala/chiselTests/BlackBox.scala @@ -2,14 +2,10 @@ package chiselTests -import java.io.File - -import org.scalatest._ import chisel3._ import chisel3.experimental._ import chisel3.testers.BasicTester import chisel3.util._ -//import chisel3.core.ExplicitCompileOptions.Strict class BlackBoxInverter extends BlackBox { val io = IO(new Bundle() { @@ -176,7 +172,7 @@ class BlackBoxSpec extends ChiselFlatSpec { elaborate(new Module { val io = IO(new Bundle { }) val m = Module(new BlackBoxPassthrough) - assert(chisel3.experimental.DataMirror.modulePorts(m) == Seq( + assert(DataMirror.modulePorts(m) == Seq( "in" -> m.io.in, "out" -> m.io.out)) }) } diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala index 80bea3a0..70bd0166 100644 --- a/src/test/scala/chiselTests/BoringUtilsSpec.scala +++ b/src/test/scala/chiselTests/BoringUtilsSpec.scala @@ -2,8 +2,6 @@ package chiselTests -import java.io.File - import chisel3._ import chisel3.util.Counter import chisel3.testers.BasicTester diff --git a/src/test/scala/chiselTests/BundleLiteralSpec.scala b/src/test/scala/chiselTests/BundleLiteralSpec.scala index 2a6c53d5..aa1dbc0f 100644 --- a/src/test/scala/chiselTests/BundleLiteralSpec.scala +++ b/src/test/scala/chiselTests/BundleLiteralSpec.scala @@ -6,7 +6,7 @@ import chisel3._ import chisel3.testers.BasicTester import chisel3.experimental.RawModule import chisel3.experimental.BundleLiterals._ -import chisel3.core.BundleLiteralException +import chisel3.experimental.BundleLiteralException class BundleLiteralSpec extends ChiselFlatSpec { class MyBundle extends Bundle { diff --git a/src/test/scala/chiselTests/BundleSpec.scala b/src/test/scala/chiselTests/BundleSpec.scala index d30b64b3..c5f40c8a 100644 --- a/src/test/scala/chiselTests/BundleSpec.scala +++ b/src/test/scala/chiselTests/BundleSpec.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.core.IgnoreSeqInBundle import chisel3.testers.BasicTester trait BundleSpecUtils { diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala index 0faab9d0..56a9f1bf 100644 --- a/src/test/scala/chiselTests/BundleWire.scala +++ b/src/test/scala/chiselTests/BundleWire.scala @@ -2,10 +2,7 @@ package chiselTests import chisel3._ -import org.scalatest._ -import org.scalatest.prop._ import chisel3.testers.BasicTester -//import chisel3.core.ExplicitCompileOptions.Strict class Coord extends Bundle { val x = UInt(32.W) diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala index ff75c1a3..0a0eb3f0 100644 --- a/src/test/scala/chiselTests/ChiselSpec.scala +++ b/src/test/scala/chiselTests/ChiselSpec.scala @@ -2,7 +2,6 @@ package chiselTests -import java.io.File import org.scalatest._ import org.scalatest.prop._ import org.scalacheck._ diff --git a/src/test/scala/chiselTests/CloneModuleSpec.scala b/src/test/scala/chiselTests/CloneModuleSpec.scala index bef29fce..59ba2eb5 100644 --- a/src/test/scala/chiselTests/CloneModuleSpec.scala +++ b/src/test/scala/chiselTests/CloneModuleSpec.scala @@ -4,10 +4,8 @@ package chiselTests import chisel3._ import chisel3.util.{Queue, EnqIO, DeqIO, QueueIO, log2Ceil} -import chisel3.experimental.{CloneModuleAsRecord, MultiIOModule} +import chisel3.experimental.{CloneModuleAsRecord, IO, MultiIOModule} import chisel3.testers.BasicTester -import org.scalatest._ -import org.scalatest.prop._ class MultiIOQueue[T <: Data](gen: T, val entries: Int) extends MultiIOModule { val clk = IO(Input(Clock())) diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala index 02b35734..861b3fdd 100644 --- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala @@ -2,7 +2,7 @@ package chiselTests -import collection.immutable.ListMap +import scala.collection.immutable.ListMap // Keep Chisel._ separate from chisel3._ below object CompatibilityComponents { diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala index 57cb5ec3..ac9b6029 100644 --- a/src/test/scala/chiselTests/CompatibilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilitySpec.scala @@ -297,7 +297,7 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks // Note: This is a regression (see https://github.com/freechipsproject/chisel3/issues/668) it should "fail for Chisel types" in { import Chisel._ - an [chisel3.core.Binding.ExpectedHardwareException] should be thrownBy { + an [chisel3.ExpectedHardwareException] should be thrownBy { elaborate(new Module { val io = new Bundle { } UInt(INPUT).dir diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala index 4f647442..10be4ffb 100644 --- a/src/test/scala/chiselTests/CompileOptionsTest.scala +++ b/src/test/scala/chiselTests/CompileOptionsTest.scala @@ -3,13 +3,12 @@ package chiselTests import chisel3._ -import chisel3.core.Binding.BindingException -import chisel3.core.CompileOptions._ +import chisel3.CompileOptions._ class CompileOptionsSpec extends ChiselFlatSpec { - abstract class StrictModule extends Module()(chisel3.core.ExplicitCompileOptions.Strict) - abstract class NotStrictModule extends Module()(chisel3.core.ExplicitCompileOptions.NotStrict) + abstract class StrictModule extends Module()(chisel3.ExplicitCompileOptions.Strict) + abstract class NotStrictModule extends Module()(chisel3.ExplicitCompileOptions.NotStrict) class SmallBundle extends Bundle { val f1 = UInt(4.W) @@ -24,7 +23,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { // scalastyle:off line.size.limit "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [ChiselException] should be thrownBy { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ConnectFieldMismatchModule extends Module { val io = IO(new Bundle { @@ -38,7 +37,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module with missing bundle fields when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { - import chisel3.core.ExplicitCompileOptions.NotStrict + import chisel3.ExplicitCompileOptions.NotStrict class ConnectFieldMismatchModule extends Module { val io = IO(new Bundle { @@ -52,7 +51,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { "A Module in which a Reg is created with a bound type when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [BindingException] should be thrownBy { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class CreateRegFromBoundTypeModule extends Module { val io = IO(new Bundle { @@ -66,7 +65,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module in which a Reg is created with a bound type when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { - import chisel3.core.ExplicitCompileOptions.NotStrict + import chisel3.ExplicitCompileOptions.NotStrict class CreateRegFromBoundTypeModule extends Module { val io = IO(new Bundle { @@ -79,7 +78,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module with wrapped IO when compiled with implicit Strict.CompileOption " should "not throw an exception" in { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class RequireIOWrapModule extends Module { val io = IO(new Bundle { @@ -93,7 +92,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { "A Module with unwrapped IO when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [BindingException] should be thrownBy { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class RequireIOWrapModule extends Module { val io = new Bundle { @@ -110,7 +109,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { "A Module connecting output as source to input as sink when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [ChiselException] should be thrownBy { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class SimpleModule extends Module { val io = IO(new Bundle { @@ -127,7 +126,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module connecting output as source to input as sink when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { - import chisel3.core.ExplicitCompileOptions.NotStrict + import chisel3.ExplicitCompileOptions.NotStrict class SimpleModule extends Module { val io = IO(new Bundle { @@ -145,8 +144,8 @@ class CompileOptionsSpec extends ChiselFlatSpec { "A Module with directionless connections when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [ChiselException] should be thrownBy { // Verify we can suppress the inclusion of default compileOptions - import Chisel.{defaultCompileOptions => _, _} - import chisel3.core.ExplicitCompileOptions.Strict + import Chisel.{defaultCompileOptions => _} + import chisel3.ExplicitCompileOptions.Strict class SimpleModule extends Module { val io = IO(new Bundle { @@ -167,7 +166,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } "A Module with directionless connections when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in { - import chisel3.core.ExplicitCompileOptions.NotStrict + import chisel3.ExplicitCompileOptions.NotStrict class SimpleModule extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala index 56a7aa3d..d0535ae2 100644 --- a/src/test/scala/chiselTests/ComplexAssign.scala +++ b/src/test/scala/chiselTests/ComplexAssign.scala @@ -2,9 +2,6 @@ package chiselTests -import org.scalatest._ -import org.scalatest.prop._ - import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala index b85d37a1..34fdec8e 100644 --- a/src/test/scala/chiselTests/Counter.scala +++ b/src/test/scala/chiselTests/Counter.scala @@ -2,9 +2,6 @@ package chiselTests -import org.scalatest._ -import org.scalatest.prop._ - import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala index ff6c83b9..59ad6324 100644 --- a/src/test/scala/chiselTests/Decoder.scala +++ b/src/test/scala/chiselTests/Decoder.scala @@ -2,8 +2,6 @@ package chiselTests -import org.scalatest._ -import org.scalatest.prop._ import org.scalacheck._ import chisel3._ diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala index 0b0807fd..4c5e819d 100644 --- a/src/test/scala/chiselTests/Direction.scala +++ b/src/test/scala/chiselTests/Direction.scala @@ -4,7 +4,7 @@ package chiselTests import org.scalatest._ import chisel3._ -import chisel3.util.Decoupled +import chisel3.experimental.RawModule class DirectionedBundle extends Bundle { val in = Input(UInt(32.W)) @@ -128,7 +128,6 @@ class DirectionSpec extends ChiselPropSpec with Matchers { } import chisel3.experimental.{MultiIOModule, DataMirror, Direction, RawModule} - import chisel3.core.SpecifiedDirection property("Directions should be preserved through cloning and binding of Bundles") { elaborate(new MultiIOModule { diff --git a/src/test/scala/chiselTests/DontTouchSpec.scala b/src/test/scala/chiselTests/DontTouchSpec.scala index f916b20a..4b1bce8e 100644 --- a/src/test/scala/chiselTests/DontTouchSpec.scala +++ b/src/test/scala/chiselTests/DontTouchSpec.scala @@ -4,7 +4,6 @@ package chiselTests import chisel3._ import chisel3.experimental.dontTouch -import firrtl.{FirrtlExecutionSuccess, Transform} class HasDeadCodeChild(withDontTouch: Boolean) extends Module { val io = IO(new Bundle { @@ -52,7 +51,7 @@ class DontTouchSpec extends ChiselFlatSpec { } } "Dont touch" should "only work on bound hardware" in { - a [chisel3.core.Binding.BindingException] should be thrownBy { + a [chisel3.BindingException] should be thrownBy { elaborate(new Module { val io = IO(new Bundle { }) dontTouch(new Bundle { val a = UInt(32.W) } ) diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala index db569233..d6bfc94d 100644 --- a/src/test/scala/chiselTests/EnableShiftRegister.scala +++ b/src/test/scala/chiselTests/EnableShiftRegister.scala @@ -2,7 +2,6 @@ package chiselTests import chisel3._ -import chisel3.testers.BasicTester class EnableShiftRegister extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/ExtModule.scala b/src/test/scala/chiselTests/ExtModule.scala index 5d5b51f9..0349d180 100644 --- a/src/test/scala/chiselTests/ExtModule.scala +++ b/src/test/scala/chiselTests/ExtModule.scala @@ -2,17 +2,16 @@ package chiselTests -import java.io.File - -import org.scalatest._ import chisel3._ import chisel3.experimental._ import chisel3.testers.BasicTester -import chisel3.util._ // Avoid collisions with regular BlackBox tests by putting ExtModule blackboxes // in their own scope. package ExtModule { + + import chisel3.experimental.ExtModule + class BlackBoxInverter extends ExtModule { val in = IO(Input(Bool())) val out = IO(Output(Bool())) @@ -72,7 +71,7 @@ class ExtModuleSpec extends ChiselFlatSpec { elaborate(new Module { val io = IO(new Bundle { }) val m = Module(new ExtModule.BlackBoxPassthrough) - assert(chisel3.experimental.DataMirror.modulePorts(m) == Seq( + assert(DataMirror.modulePorts(m) == Seq( "in" -> m.in, "out" -> m.out)) }) } diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala index 499ab591..5c9641be 100644 --- a/src/test/scala/chiselTests/GCD.scala +++ b/src/test/scala/chiselTests/GCD.scala @@ -4,8 +4,6 @@ package chiselTests import chisel3._ import chisel3.testers.BasicTester -import org.scalatest._ -import org.scalatest.prop._ class GCD extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala index 1da3d166..57596b49 100644 --- a/src/test/scala/chiselTests/Harness.scala +++ b/src/test/scala/chiselTests/Harness.scala @@ -2,10 +2,8 @@ package chiselTests -import chisel3.testers.BasicTester -import org.scalatest._ -import org.scalatest.prop._ import java.io.File + import firrtl.util.BackendCompilationUtilities class HarnessSpec extends ChiselPropSpec diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala index af64c9f3..55d9e947 100644 --- a/src/test/scala/chiselTests/IOCompatibility.scala +++ b/src/test/scala/chiselTests/IOCompatibility.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.core.Binding.BindingException import org.scalatest._ class IOCSimpleIO extends Bundle { diff --git a/src/test/scala/chiselTests/InlineSpec.scala b/src/test/scala/chiselTests/InlineSpec.scala index 0bb29fdf..3cc83bb9 100644 --- a/src/test/scala/chiselTests/InlineSpec.scala +++ b/src/test/scala/chiselTests/InlineSpec.scala @@ -4,15 +4,11 @@ package chiselTests import chisel3._ import chisel3.util.experimental.{InlineInstance, FlattenInstance} -import chisel3.internal.firrtl.Circuit import firrtl.FirrtlExecutionSuccess import firrtl.passes.InlineAnnotation -import firrtl.annotations.Annotation import firrtl.transforms.FlattenAnnotation import firrtl.analyses.InstanceGraph import firrtl.{ir => fir} -import firrtl.WDefInstance -import firrtl.Mappers._ import org.scalatest.{FreeSpec, Matchers} class InlineSpec extends FreeSpec with ChiselRunners with Matchers { diff --git a/src/test/scala/chiselTests/InstanceNameSpec.scala b/src/test/scala/chiselTests/InstanceNameSpec.scala index 7bb91b94..afd9af93 100644 --- a/src/test/scala/chiselTests/InstanceNameSpec.scala +++ b/src/test/scala/chiselTests/InstanceNameSpec.scala @@ -4,8 +4,6 @@ package chiselTests import chisel3._ import chisel3.util.Queue -import chisel3.experimental.{DataMirror, FixedPoint} -import chisel3.testers.BasicTester class InstanceNameModule extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/InvalidateAPISpec.scala b/src/test/scala/chiselTests/InvalidateAPISpec.scala index 8dfb078b..a285b4c8 100644 --- a/src/test/scala/chiselTests/InvalidateAPISpec.scala +++ b/src/test/scala/chiselTests/InvalidateAPISpec.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.core.BiConnect.BiConnectException import chisel3.util.Counter import firrtl.passes.CheckInitialization.RefNotInitializedException import firrtl.util.BackendCompilationUtilities @@ -23,7 +22,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila // scalastyle:off line.size.limit property("an output connected to DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithDontCare extends Module { val io = IO(new TrivialInterface) io.out := DontCare @@ -34,7 +33,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should NOT emit a Firrtl \"is invalid\" with Strict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithoutDontCare extends Module { val io = IO(new TrivialInterface) io.out := io.in @@ -44,7 +43,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should emit a Firrtl \"is invalid\" with NotStrict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.NotStrict + import chisel3.ExplicitCompileOptions.NotStrict class ModuleWithoutDontCare extends Module { val io = IO(new TrivialInterface) io.out := io.in @@ -54,7 +53,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("a bundle with a DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithoutDontCare extends Module { val io = IO(new TrivialInterface) io <> DontCare @@ -65,7 +64,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("a Vec with a DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions and bulk connect") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict val nElements = 5 class ModuleWithoutDontCare extends Module { val io = IO(new Bundle { @@ -79,7 +78,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("a Vec with a DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions and mono connect") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict val nElements = 5 class ModuleWithoutDontCare extends Module { val io = IO(new Bundle { @@ -93,7 +92,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("a DontCare cannot be a connection sink (LHS) for := ") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithDontCareSink extends Module { val io = IO(new TrivialInterface) DontCare := io.in @@ -105,7 +104,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("a DontCare cannot be a connection sink (LHS) for <>") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithDontCareSink extends Module { val io = IO(new TrivialInterface) DontCare <> io.in @@ -117,7 +116,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("FIRRTL should complain about partial initialization with Strict CompileOptions and conditional connect") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithIncompleteAssignment extends Module { val io = IO(new Bundle { val out = Output(Bool()) @@ -134,7 +133,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("FIRRTL should not complain about partial initialization with Strict CompileOptions and conditional connect after unconditional connect") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithUnconditionalAssignment extends Module { val io = IO(new Bundle { val out = Output(Bool()) @@ -149,7 +148,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("FIRRTL should not complain about partial initialization with Strict CompileOptions and conditional connect with otherwise clause") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithConditionalAndOtherwiseAssignment extends Module { val io = IO(new Bundle { val out = Output(Bool()) @@ -166,9 +165,9 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should NOT emit a Firrtl \"is invalid\" with overriden NotStrict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.NotStrict + import chisel3.ExplicitCompileOptions.NotStrict class ModuleWithoutDontCare extends Module { - override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true) + override val compileOptions = chisel3.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true) val io = IO(new TrivialInterface) io.out := io.in } @@ -177,8 +176,8 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should NOT emit a Firrtl \"is invalid\" with overriden NotStrict CompileOptions module definition") { - import chisel3.core.ExplicitCompileOptions.NotStrict - abstract class ExplicitInvalidateModule extends Module()(chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)) + import chisel3.ExplicitCompileOptions.NotStrict + abstract class ExplicitInvalidateModule extends Module()(chisel3.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)) class ModuleWithoutDontCare extends ExplicitInvalidateModule { val io = IO(new TrivialInterface) io.out := io.in @@ -188,9 +187,9 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should emit a Firrtl \"is invalid\" with overriden Strict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithoutDontCare extends Module { - override val compileOptions = chisel3.core.ExplicitCompileOptions.Strict.copy(explicitInvalidate = false) + override val compileOptions = chisel3.ExplicitCompileOptions.Strict.copy(explicitInvalidate = false) val io = IO(new TrivialInterface) io.out := io.in } @@ -199,8 +198,8 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should emit a Firrtl \"is invalid\" with overriden Strict CompileOptions module definition") { - import chisel3.core.ExplicitCompileOptions.Strict - abstract class ImplicitInvalidateModule extends Module()(chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = false)) + import chisel3.ExplicitCompileOptions.Strict + abstract class ImplicitInvalidateModule extends Module()(chisel3.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = false)) class ModuleWithoutDontCare extends ImplicitInvalidateModule { val io = IO(new TrivialInterface) io.out := io.in diff --git a/src/test/scala/chiselTests/LiteralExtractorSpec.scala b/src/test/scala/chiselTests/LiteralExtractorSpec.scala index c2d84831..533de888 100644 --- a/src/test/scala/chiselTests/LiteralExtractorSpec.scala +++ b/src/test/scala/chiselTests/LiteralExtractorSpec.scala @@ -3,11 +3,9 @@ package chiselTests import chisel3._ -import chisel3.core.FixedPoint -import chisel3.experimental.RawModule +import chisel3.experimental.{FixedPoint, RawModule} import chisel3.experimental.BundleLiterals._ import chisel3.testers.BasicTester -import org.scalatest._ class LiteralExtractorSpec extends ChiselFlatSpec { "litValue" should "return the literal value" in { @@ -70,15 +68,15 @@ class LiteralExtractorSpec extends ChiselFlatSpec { // the following errors with "assertion failed" println(outsideLiteral === insideLiteral) // scalastyle:ignore regex - // chisel3.core.assert(outsideLiteral === insideLiteral) + // chisel3.assert(outsideLiteral === insideLiteral) // the following lines of code error - // with "chisel3.core.BundleLitBinding cannot be cast to chisel3.core.ElementLitBinding" + // with "chisel3.internal.BundleLitBinding cannot be cast to chisel3.internal.ElementLitBinding" - chisel3.core.assert(outsideLiteral.x === insideLiteral.x) - chisel3.core.assert(outsideLiteral.y === insideLiteral.y) - chisel3.core.assert(outsideLiteral.x === 7.S) - chisel3.core.assert(outsideLiteral.y === 6.125.F(4.BP)) + chisel3.assert(outsideLiteral.x === insideLiteral.x) + chisel3.assert(outsideLiteral.y === insideLiteral.y) + chisel3.assert(outsideLiteral.x === 7.S) + chisel3.assert(outsideLiteral.y === 6.125.F(4.BP)) stop() } diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala index 93902d22..3264f4dd 100644 --- a/src/test/scala/chiselTests/MemorySearch.scala +++ b/src/test/scala/chiselTests/MemorySearch.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.testers.BasicTester class MemorySearch extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/MixedVecSpec.scala b/src/test/scala/chiselTests/MixedVecSpec.scala index 3bedf87f..5dd30270 100644 --- a/src/test/scala/chiselTests/MixedVecSpec.scala +++ b/src/test/scala/chiselTests/MixedVecSpec.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.core.Binding import chisel3.testers.BasicTester import chisel3.util._ import org.scalacheck.Shrink @@ -209,21 +208,21 @@ class MixedVecSpec extends ChiselPropSpec { } property("MixedVecs should not be able to take hardware types") { - a [Binding.ExpectedChiselTypeException] should be thrownBy { + a [ExpectedChiselTypeException] should be thrownBy { elaborate(new Module { val io = IO(new Bundle {}) val hw = Wire(MixedVec(Seq(UInt(8.W), Bool()))) val illegal = MixedVec(hw) }) } - a [Binding.ExpectedChiselTypeException] should be thrownBy { + a [ExpectedChiselTypeException] should be thrownBy { elaborate(new Module { val io = IO(new Bundle {}) val hw = Reg(MixedVec(Seq(UInt(8.W), Bool()))) val illegal = MixedVec(hw) }) } - a [Binding.ExpectedChiselTypeException] should be thrownBy { + a [ExpectedChiselTypeException] should be thrownBy { elaborate(new Module { val io = IO(new Bundle { val v = Input(MixedVec(Seq(UInt(8.W), Bool()))) diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 46e60064..ed624f0c 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -3,6 +3,7 @@ package chiselTests import chisel3._ +import chisel3.experimental.DataMirror class SimpleIO extends Bundle { val in = Input(UInt(32.W)) @@ -145,7 +146,7 @@ class ModuleSpec extends ChiselPropSpec { val a = IO(UInt(8.W)) val b = IO(Bool()) }) - assert(chisel3.experimental.DataMirror.modulePorts(m) == Seq( + assert(DataMirror.modulePorts(m) == Seq( "clock" -> m.clock, "reset" -> m.reset, "a" -> m.a, "b" -> m.b)) }) diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala index 38d010ee..e3501ad3 100644 --- a/src/test/scala/chiselTests/MulLookup.scala +++ b/src/test/scala/chiselTests/MulLookup.scala @@ -3,8 +3,6 @@ package chiselTests import chisel3._ -import org.scalatest._ -import org.scalatest.prop._ import chisel3.testers.BasicTester class MulLookup(val w: Int) extends Module { diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index 745e25de..8da5bc42 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -2,8 +2,6 @@ package chiselTests -import org.scalatest._ - import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ diff --git a/src/test/scala/chiselTests/NamingAnnotationTest.scala b/src/test/scala/chiselTests/NamingAnnotationTest.scala index aae9123e..82a5c109 100644 --- a/src/test/scala/chiselTests/NamingAnnotationTest.scala +++ b/src/test/scala/chiselTests/NamingAnnotationTest.scala @@ -3,11 +3,8 @@ package chiselTests import chisel3._ +import chisel3.experimental.{MultiIOModule, chiselName} import chisel3.internal.InstanceId -import chisel3.experimental.{chiselName, dump, MultiIOModule} -import org.scalatest._ -import org.scalatest.prop._ -import chisel3.testers.BasicTester import scala.collection.mutable.ListBuffer diff --git a/src/test/scala/chiselTests/OneHotMuxSpec.scala b/src/test/scala/chiselTests/OneHotMuxSpec.scala index be252bef..7476ebe2 100644 --- a/src/test/scala/chiselTests/OneHotMuxSpec.scala +++ b/src/test/scala/chiselTests/OneHotMuxSpec.scala @@ -2,9 +2,9 @@ package chiselTests -import Chisel.testers.BasicTester import chisel3._ import chisel3.experimental.FixedPoint +import chisel3.testers.BasicTester import chisel3.util.{Mux1H, UIntToOH} import org.scalatest._ diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala index 03b08385..b9b50baa 100644 --- a/src/test/scala/chiselTests/OptionBundle.scala +++ b/src/test/scala/chiselTests/OptionBundle.scala @@ -2,7 +2,6 @@ package chiselTests -import org.scalatest._ import chisel3._ import chisel3.testers.BasicTester diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala index 028b5baf..a04bf830 100644 --- a/src/test/scala/chiselTests/ParameterizedModule.scala +++ b/src/test/scala/chiselTests/ParameterizedModule.scala @@ -2,7 +2,6 @@ package chiselTests -import org.scalatest._ import chisel3._ import chisel3.testers.BasicTester diff --git a/src/test/scala/chiselTests/PopCount.scala b/src/test/scala/chiselTests/PopCount.scala index d9b3b837..1d6c86b9 100644 --- a/src/test/scala/chiselTests/PopCount.scala +++ b/src/test/scala/chiselTests/PopCount.scala @@ -4,8 +4,6 @@ package chiselTests import chisel3._ import chisel3.util.PopCount -import org.scalatest._ -import org.scalatest.prop._ import chisel3.testers.BasicTester class PopCountTester(n: Int) extends BasicTester { diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala index 7ba4bf5d..aeb92532 100644 --- a/src/test/scala/chiselTests/PrintableSpec.scala +++ b/src/test/scala/chiselTests/PrintableSpec.scala @@ -3,8 +3,6 @@ package chiselTests import org.scalatest.{FlatSpec, Matchers} -import scala.collection.mutable - import chisel3._ import chisel3.testers.BasicTester diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala index c1f084c6..3927ffa8 100644 --- a/src/test/scala/chiselTests/Printf.scala +++ b/src/test/scala/chiselTests/Printf.scala @@ -2,9 +2,7 @@ package chiselTests -import org.scalatest._ import chisel3._ -import chisel3.util._ import chisel3.testers.BasicTester class SinglePrintfTester() extends BasicTester { diff --git a/src/test/scala/chiselTests/QueueSpec.scala b/src/test/scala/chiselTests/QueueSpec.scala index 994f3e6d..c26e9485 100644 --- a/src/test/scala/chiselTests/QueueSpec.scala +++ b/src/test/scala/chiselTests/QueueSpec.scala @@ -2,8 +2,6 @@ package chiselTests -import org.scalatest._ -import org.scalatest.prop._ import org.scalacheck._ import chisel3._ diff --git a/src/test/scala/chiselTests/RebindingSpec.scala b/src/test/scala/chiselTests/RebindingSpec.scala index dddf26b6..f7a79ace 100644 --- a/src/test/scala/chiselTests/RebindingSpec.scala +++ b/src/test/scala/chiselTests/RebindingSpec.scala @@ -6,7 +6,7 @@ import chisel3._ class RebindingSpec extends ChiselFlatSpec { "Rebinding a literal" should "fail" in { - a [chisel3.core.Binding.BindingException] should be thrownBy { + a [BindingException] should be thrownBy { elaborate { new Module { val io = IO(new Bundle { val a = 4.U @@ -16,7 +16,7 @@ class RebindingSpec extends ChiselFlatSpec { } "Rebinding a hardware type" should "fail" in { - a [chisel3.core.Binding.BindingException] should be thrownBy { + a [BindingException] should be thrownBy { elaborate { new Module { val io = IO(new Bundle { val a = Reg(UInt(32.W)) diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index 7de85d04..c4df0742 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -2,12 +2,9 @@ package chiselTests -import firrtl.ir.Input -import org.scalatest._ -import org.scalatest.prop._ import chisel3._ import chisel3.util._ -import chisel3.core.DataMirror +import chisel3.experimental.DataMirror import chisel3.testers.BasicTester class RegSpec extends ChiselFlatSpec { diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 9f17c741..3c13273a 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -2,8 +2,6 @@ package chiselTests -import scala.collection.mutable.Stack - import chisel3._ import chisel3.util._ diff --git a/src/test/scala/chiselTests/Stop.scala b/src/test/scala/chiselTests/Stop.scala index 136fafc8..d912fe77 100644 --- a/src/test/scala/chiselTests/Stop.scala +++ b/src/test/scala/chiselTests/Stop.scala @@ -2,7 +2,6 @@ package chiselTests -import org.scalatest._ import chisel3._ import chisel3.testers.BasicTester diff --git a/src/test/scala/chiselTests/StrongEnum.scala b/src/test/scala/chiselTests/StrongEnum.scala index 6c87aee3..5e7ca2e1 100644 --- a/src/test/scala/chiselTests/StrongEnum.scala +++ b/src/test/scala/chiselTests/StrongEnum.scala @@ -245,7 +245,6 @@ class WidthTester extends BasicTester { } class StrongEnumFSMTester extends BasicTester { - import StrongEnumFSM.State import StrongEnumFSM.State._ val dut = Module(new StrongEnumFSM) diff --git a/src/test/scala/chiselTests/SwitchSpec.scala b/src/test/scala/chiselTests/SwitchSpec.scala index 81cf690a..2991a928 100644 --- a/src/test/scala/chiselTests/SwitchSpec.scala +++ b/src/test/scala/chiselTests/SwitchSpec.scala @@ -4,7 +4,6 @@ package chiselTests import chisel3._ import chisel3.util._ -import chisel3.testers.BasicTester class SwitchSpec extends ChiselFlatSpec { "switch" should "require literal conditions" in { diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index c09189e6..a0fda1ec 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -2,9 +2,6 @@ package chiselTests -import org.scalatest._ -import org.scalatest.prop._ - import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala index a7137699..7c571837 100644 --- a/src/test/scala/chiselTests/TesterDriverSpec.scala +++ b/src/test/scala/chiselTests/TesterDriverSpec.scala @@ -5,7 +5,6 @@ package chiselTests import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ -//import chisel3.core.ExplicitCompileOptions.Strict /** Extend BasicTester with a simple circuit and finish method. TesterDriver will call the * finish method after the FinishTester's constructor has completed, which will alter the diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index d8fde208..0884ad37 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -3,8 +3,6 @@ package chiselTests import chisel3._ -import chisel3.experimental.RawModule -import chisel3.core.Binding.BindingException import chisel3.testers.BasicTester import chisel3.util._ import org.scalacheck.Shrink diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala index 58d5a1bd..df9c8cce 100644 --- a/src/test/scala/chiselTests/When.scala +++ b/src/test/scala/chiselTests/When.scala @@ -2,8 +2,6 @@ package chiselTests -import org.scalatest._ - import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ diff --git a/src/test/scala/cookbook/RegOfVec.scala b/src/test/scala/cookbook/RegOfVec.scala index fee7f2e1..e5bb1ca8 100644 --- a/src/test/scala/cookbook/RegOfVec.scala +++ b/src/test/scala/cookbook/RegOfVec.scala @@ -7,7 +7,7 @@ import chisel3._ /* ### How do I create a Reg of type Vec? * * For information, please see the API documentation for Vec - * (https://chisel.eecs.berkeley.edu/api/index.html#chisel3.core.Vec) + * (https://chisel.eecs.berkeley.edu/api/index.html#chisel3.Vec) */ class RegOfVec extends CookbookTester(2) { // Reg of Vec of 32-bit UInts without initialization diff --git a/src/test/scala/cookbook/UInt2VecOfBool.scala b/src/test/scala/cookbook/UInt2VecOfBool.scala index 10250ad5..1f6d1006 100644 --- a/src/test/scala/cookbook/UInt2VecOfBool.scala +++ b/src/test/scala/cookbook/UInt2VecOfBool.scala @@ -6,7 +6,7 @@ import chisel3._ /* ### How do I create a Vec of Bools from a UInt? * - * Use the builtin function [[chisel3.core.Bits.asBools]] to create a Scala Seq of Bool, + * Use the builtin function [[chisel3.Bits.asBools]] to create a Scala Seq of Bool, * then wrap the resulting Seq in Vec(...) */ class UInt2VecOfBool extends CookbookTester(1) { |