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Diffstat (limited to 'src/test/scala/chiselTests/Module.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Module.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 46e60064..ed624f0c 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -3,6 +3,7 @@ package chiselTests import chisel3._ +import chisel3.experimental.DataMirror class SimpleIO extends Bundle { val in = Input(UInt(32.W)) @@ -145,7 +146,7 @@ class ModuleSpec extends ChiselPropSpec { val a = IO(UInt(8.W)) val b = IO(Bool()) }) - assert(chisel3.experimental.DataMirror.modulePorts(m) == Seq( + assert(DataMirror.modulePorts(m) == Seq( "clock" -> m.clock, "reset" -> m.reset, "a" -> m.a, "b" -> m.b)) }) |