diff options
Diffstat (limited to 'src/test/scala/chiselTests/InvalidateAPISpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/InvalidateAPISpec.scala | 39 |
1 files changed, 19 insertions, 20 deletions
diff --git a/src/test/scala/chiselTests/InvalidateAPISpec.scala b/src/test/scala/chiselTests/InvalidateAPISpec.scala index 8dfb078b..a285b4c8 100644 --- a/src/test/scala/chiselTests/InvalidateAPISpec.scala +++ b/src/test/scala/chiselTests/InvalidateAPISpec.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.core.BiConnect.BiConnectException import chisel3.util.Counter import firrtl.passes.CheckInitialization.RefNotInitializedException import firrtl.util.BackendCompilationUtilities @@ -23,7 +22,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila // scalastyle:off line.size.limit property("an output connected to DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithDontCare extends Module { val io = IO(new TrivialInterface) io.out := DontCare @@ -34,7 +33,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should NOT emit a Firrtl \"is invalid\" with Strict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithoutDontCare extends Module { val io = IO(new TrivialInterface) io.out := io.in @@ -44,7 +43,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should emit a Firrtl \"is invalid\" with NotStrict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.NotStrict + import chisel3.ExplicitCompileOptions.NotStrict class ModuleWithoutDontCare extends Module { val io = IO(new TrivialInterface) io.out := io.in @@ -54,7 +53,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("a bundle with a DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithoutDontCare extends Module { val io = IO(new TrivialInterface) io <> DontCare @@ -65,7 +64,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("a Vec with a DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions and bulk connect") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict val nElements = 5 class ModuleWithoutDontCare extends Module { val io = IO(new Bundle { @@ -79,7 +78,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("a Vec with a DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions and mono connect") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict val nElements = 5 class ModuleWithoutDontCare extends Module { val io = IO(new Bundle { @@ -93,7 +92,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("a DontCare cannot be a connection sink (LHS) for := ") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithDontCareSink extends Module { val io = IO(new TrivialInterface) DontCare := io.in @@ -105,7 +104,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("a DontCare cannot be a connection sink (LHS) for <>") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithDontCareSink extends Module { val io = IO(new TrivialInterface) DontCare <> io.in @@ -117,7 +116,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("FIRRTL should complain about partial initialization with Strict CompileOptions and conditional connect") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithIncompleteAssignment extends Module { val io = IO(new Bundle { val out = Output(Bool()) @@ -134,7 +133,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("FIRRTL should not complain about partial initialization with Strict CompileOptions and conditional connect after unconditional connect") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithUnconditionalAssignment extends Module { val io = IO(new Bundle { val out = Output(Bool()) @@ -149,7 +148,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("FIRRTL should not complain about partial initialization with Strict CompileOptions and conditional connect with otherwise clause") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithConditionalAndOtherwiseAssignment extends Module { val io = IO(new Bundle { val out = Output(Bool()) @@ -166,9 +165,9 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should NOT emit a Firrtl \"is invalid\" with overriden NotStrict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.NotStrict + import chisel3.ExplicitCompileOptions.NotStrict class ModuleWithoutDontCare extends Module { - override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true) + override val compileOptions = chisel3.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true) val io = IO(new TrivialInterface) io.out := io.in } @@ -177,8 +176,8 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should NOT emit a Firrtl \"is invalid\" with overriden NotStrict CompileOptions module definition") { - import chisel3.core.ExplicitCompileOptions.NotStrict - abstract class ExplicitInvalidateModule extends Module()(chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)) + import chisel3.ExplicitCompileOptions.NotStrict + abstract class ExplicitInvalidateModule extends Module()(chisel3.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)) class ModuleWithoutDontCare extends ExplicitInvalidateModule { val io = IO(new TrivialInterface) io.out := io.in @@ -188,9 +187,9 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should emit a Firrtl \"is invalid\" with overriden Strict CompileOptions") { - import chisel3.core.ExplicitCompileOptions.Strict + import chisel3.ExplicitCompileOptions.Strict class ModuleWithoutDontCare extends Module { - override val compileOptions = chisel3.core.ExplicitCompileOptions.Strict.copy(explicitInvalidate = false) + override val compileOptions = chisel3.ExplicitCompileOptions.Strict.copy(explicitInvalidate = false) val io = IO(new TrivialInterface) io.out := io.in } @@ -199,8 +198,8 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila } property("an output without a DontCare should emit a Firrtl \"is invalid\" with overriden Strict CompileOptions module definition") { - import chisel3.core.ExplicitCompileOptions.Strict - abstract class ImplicitInvalidateModule extends Module()(chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = false)) + import chisel3.ExplicitCompileOptions.Strict + abstract class ImplicitInvalidateModule extends Module()(chisel3.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = false)) class ModuleWithoutDontCare extends ImplicitInvalidateModule { val io = IO(new TrivialInterface) io.out := io.in |