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AgeCommit message (Expand)Author
2018-06-28Protobuf (#832)Jack Koenig
2017-06-27Emitting reg update mux tree, only walk netlist for wires and nodesJack Koenig
2016-12-08Clk2clock - rename the implicit "clk" module input "clock" (#387)Jim Lawson
2016-08-17Change RW port names (#236)Angie Wang
2016-08-15Remove stanza (#231)Adam Izraelevitz
2016-05-24Add integration test for single-ported memoryjackkoenig
2016-04-08Fixed bug in Remove Accesses where a WSubAccess's index was not checked for a...Adam Izraelevitz
2016-03-15Revamp string literal handlingjackkoenig
2016-03-10Add support for right shift by amount larger than argument widthjackkoenig
2016-03-03Add some integration tests: successful compilation and executionjackkoenig
2016-02-24Fixed printf bugs in scala and stanza versions. Required special casing print...Adam Izraelevitz
2016-02-09Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2016-02-09Added remaining check passes. Ready for open sourcingazidar
2016-02-09Bug fixes, close to getting correct rocket-firrtl.fir throughazidar
2016-02-09Added Lower Types.azidar
2016-02-09Added test for UInt/SInts that take stringsazidar
2016-02-09Changed stanza output of UInt/SInt to include widths. Made tests match accord...azidar
2016-02-08Escape quotes in strings before emitting as VerilogPalmer Dabbelt
2016-01-29Update parser tests to match 0.2.0 spec, Scala FIRRTL passes these testsJack
2016-01-28Fixed rdwr and wr to verilog testsazidar
2016-01-28Fixed bug where subaccess indexes were being classified as female,azidar
2016-01-28Changed rmode to wmodeazidar
2016-01-28Use IsInvalid instead of Poisons in chirrtl -> firrtl transformazidar
2016-01-28Added tests for previous commitazidar
2016-01-28Added addw to working ir as an optimized verilog emissionazidar
2016-01-28Fixed bug and updated test for changing mod to remazidar
2016-01-28Updated all tests to passazidar
2016-01-28Changed register syntax for optional reset and init valuesazidar
2016-01-27Reworked readwriter typesazidar
2016-01-27Fixed additional tests and inferring rdwr ports in chirrtljackkoenig
2016-01-25Fixed bug where poisons were not being declaredazidar
2016-01-25Added verilog rename passazidar
2016-01-25Added isinvalid and validifazidar
2016-01-25Fixed support for muxes and nodes with passive aggregate typesazidar
2016-01-25Fixed one more testazidar
2016-01-25Changed tests to pass with change to postfix of generated nameazidar
2016-01-24Fixed tests that broke from changing verilog backend and removing mask from w...azidar
2016-01-24Added muxing on passive aggregate typesazidar
2016-01-24Added DefMemory to CInfer Typesazidar
2016-01-23Fixed bug where the write mask wasn't being generated correctlyazidar
2016-01-23Added inference to mportsazidar
2016-01-23Added prefix checker, now compliant with firrtl specazidar
2016-01-23Changed chirrtl to not require known mask valuesazidar
2016-01-17Fixed error where memory of size 1 would create an index of size 0. This can ...azidar
2016-01-17Added check for uint on access index typeazidar
2016-01-17BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed testsazidar
2016-01-16Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignoreazidar
2016-01-16Fixed all tests so they either pass are marked as expected failuresazidar
2016-01-16Updated passes so they test new-memazidar
2016-01-16Fixed a testazidar
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