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AgeCommit message (Expand)Author
2016-01-27Reworked readwriter typesazidar
2016-01-25Added verilog rename passazidar
2016-01-25Added isinvalid and validifazidar
2016-01-24Added muxing on passive aggregate typesazidar
2016-01-17Fixed error where memory of size 1 would create an index of size 0. This can ...azidar
2016-01-16Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignoreazidar
2016-01-16Fixed all tests so they either pass are marked as expected failuresazidar
2016-01-16Fixed a bunch of tests, and minor bugsazidar
2016-01-16WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl...azidar
2016-01-16Finished supporting nested accesses. Required some nuianced thinking. Pass al...azidar
2016-01-16WIP, hit semantic bug in WSubAccessazidar
2016-01-16New memory works with verilog. Slowly changing tests and fixing bugs.azidar
2016-01-16Finished adding clocks to Stop and Printazidar
2015-10-07Added Printf and Stop to firrtl. #23 #24.azidar
2015-09-30Make Link.fir reference relative path, so it doesn't need someone's particula...ducky
2015-09-24Updated conditional read exampleazidar
2015-09-01Added a conditional readport example, with new idea of representing a read en...azidar
2015-08-24Changed all tests to use verilog backend.azidar
2015-08-20Added tests, cleaned up repoazidar
2015-08-20Added Poison node. Includes tests. #26.azidar
2015-08-17Removed leading zeros from UInt constantsazidar
2015-08-03Changed name mangling to use _ as a delin. Fixed bug in checking forazidar
2015-07-31Added errors for bulk connects where field names match but types/flips don'tazidar
2015-07-31Updated tests to pipe from stderr to stdoutazidar
2015-07-30Updated error and feature tests. Fixed bug in detecting incorrect gendersazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added te...azidar
2015-07-14Added clock supportazidar
2015-07-14Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. A...azidar
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ...azidar
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ...azidar
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
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