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2016-11-09Bugfix: removed recursive removal in infer widthsazidar
This will certainly lead to more uninferred width errors, but now widths that were previously incorrectly inferred are now correctly uninferred. An example is: reg r : UInt, clock with: (reset => (reset, UInt<2>(3))) node x = add(r, r) r <= x Here, r's width follows the following formula, which cannot be solved: rWidth >= max(max(rWidth, rWidth) + 1, 2)
2016-11-07Clock List Transform (#365)Adam Izraelevitz
Added clocklist transform
2016-11-07Fix annotations (#366)Adam Izraelevitz
getMyAnnotations now returns Seq[Annotation] Changed test to check number of annotations is the same
2016-11-07make default dir be current directory (#361)Chick Markley
2016-11-07Added underscore to GEN, now its _GEN (#362)Adam Izraelevitz
Prefix temporary names with underscores so Verilator won't trace them Use verilator argument "--trace-underscore" if you want to trace these signals
2016-11-05Fix CHIRRTL bugs (#355)Donggyu
* handle uninferred ports gracefully in RemoveCHIRRTL memory port directions are not inferred during CInferMDir if not being used, so handle them properly in RemoveCHIRRTL * fix CInferTypes
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-11-04Add a pass to deduplicate modulesazidar
2016-11-04Refactor Compilers and Transformsjackkoenig
* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers * Transforms define inputForm and outputForm * Custom transforms can be inserted at runtime into compiler or the Driver * Current "built-in" custom transforms handled via above mechanism * Verilog-specific passes moved to the Verilog emitter
2016-11-03Added Legalize to MiddleToLowFirrtlazidar
Makes low firrtl more like a netlist, should probably update spec
2016-11-01Fix Match Error in Check Types on Partial Connect (#359)Jack Koenig
Fixes #329
2016-11-01fix bug. remove spurious connect that reassigns node (#358)Scott Beamer
2016-10-31Fixed Verilog emission of andr, orr, and xorr (#357)Adam Izraelevitz
Fixed Verilog emission reduce ops with efficient implementation
2016-10-30Cleanup fixed point tests (#339)Jack Koenig
Change FixedPointMathSpec tests to use FlatSpec style instead of println Remove other printlns Remove vim comments at end of files
2016-10-30Keep package name + directory structure consistent (#354)Colin Schmidt
* Keep package name + directory structure consistent This annoyed me so heres a PR * fix InferReadWrite references * delete .ConvertFixedToSInt.scala.swo
2016-10-27Wiring (#348)Adam Izraelevitz
Added wiring pass and simple test
2016-10-26Improve reference & name resolution in ReplSeqMem (#352)Donggyu
* fix imports in InferReadWrite * improve reference & name resolution in ReplSeqMem * add comments
2016-10-26Add RawString ExtModule parameter supportjackkoenig
While unsafe, this supports Verilog parameter types. Tests now require Verilator 3.884+ to pass.
2016-10-26Add Support for Parameterized ExtModules and Name Overridejackkoenig
Adds support for Integer, Double/Real, and String parameters in external modules. Also add name field to extmodules so that emitted name can be different from Firrtl name. This is important because parameterized extmodules will frequently have differing IO even though they need to be emitted as instantiating the same Verilog module.
2016-10-26Add ExtModule Testsjackkoenig
2016-10-26Improve integration test API and add support for Verilog resourcesjackkoenig
Change integration tests to be classes that extend abstract classes. This allows them to be run in parallel. Also expand API to support Verilog resources in integration tests.
2016-10-25Logger 1 (#338)Chick Markley
* Create a simple system for executions and command line parameters New model for tracking parameters and having those parameters register scopt command to allow the parameters to be set by command line args. Create composable forms of the these parameters to allow separate elements of the chisel3 toolchain to combine these parameters Create execution return structures that simplify return values to earlier toolchain elements * just a little bit of cleanup * Fixes for Adam's comments on PR * knuckled under to self-pressure to allow former -i and -o to work * knuckled under to self-pressure to allow former -i and -o to work * show defaults for command line args with them * A couple of fixes from merging latest master * Implement a log4scala like logging system This system has the rather remarkable property that it is possible to turn it on conveniently when you want it. It also provides for class level granularity as well as the traditional Error, Warn, Info, Debug * some style fixes and change infoMode default to append per PR #328 * some style fixes and change infoMode default to append per PR #328 * support -i -o and -X a couple of indentation and spacing fixes
2016-10-24match fromBits order with toBits, toBitMask (#349)Donggyu
2016-10-23Fix bitmask (#346)Angie Wang
* toBitMask cat direction should be consistent with data * minor comment updates * moved remaining mem passes/utils to memlib * changed again so that data, mask are consistent. data element 0, bit 0 = LSB (on RHS) when concatenated
2016-10-20fix resolve memory reference (#341)Donggyu
duplcate memory detection should be in circuit-level, not in module-level
2016-10-19annotations being assembled form command line but not being passed down to ↵chick
firrtl compiler Fixes colin's problem with repl-seq-mem not creating a conf file.
2016-10-18Create a simple system for executions and command line parameters (#337)Chick Markley
Create a simple system for executions and command line parameters New model for tracking parameters and having those parameters register scopt command to allow the parameters to be set by command line args. Create composable forms of the these parameters to allow separate elements of the chisel3 toolchain to combine these parameters Create execution return structures that simplify return values to earlier toolchain elements
2016-10-17Reorganized memory blackboxing (#336)Adam Izraelevitz
* Reorganized memory blackboxing Moved to new package memlib Added comments Moved utility functions around Removed unused AnnotateValidMemConfigs.scala * Fixed tests to pass * Use DefAnnotatedMemory instead of AppendableInfo * Broke passes up into simpler passes AnnotateMemMacros -> (ToMemIR, ResolveMaskGranularity) UpdateDuplicateMemMacros -> (RenameAnnotatedMemoryPorts, ResolveMemoryReference) * Fixed to make tests run * Minor changes from code review * Removed vim comments and renamed ReplSeqMem
2016-10-17Add fixed point type (#322)Adam Izraelevitz
* WIP: Adding FixedType to Firrtl proper Got simple example running through width inference Checks should be ok Need to look into FixedLiteral more * Added simple test for fixed types * Added asFixedPoint to primops * Added tail case for FixedType * Added ConvertFixedToSInt.scala Added pass to MiddleToLowerFirrtl transform * Replace AsFixedType with AsSInt in fixed removal * Bugfix: constant from asFixed not deleted * Added unit test for bulk connect * Fixed partial connect bug #241 * Fixed missing case for FixedPoint in legalizeConnect * Add FixedMathSpec that demonstrates some problems with FixedPointMath * Fixed test and ConvertToSInt to pass. Negative binary points not easily supported, needs much more time to implement. * Refactored checking neg widths Make checking for negative binary points easier * Added tests for inferring many FixedType ops shl, shr, cat, bits, head, tail, setbp, shiftbp * Handle bpshl, bpshr, bpset in ConvertFixedToSInt Changed name from shiftbp -> bpshl, bpshr Change name from setbp -> bpset Added more tests * Added set binary point test that fails * Added simple test for zero binary point * gitignore fixes for antlr intermediate dir and intellij dir * removed unused imports retool the fixed point with zero binary point test * simplified example of inability to set binary point to zero * Temporary fix for zero-width binary point This fix allows for all widths to be zero, but since this is a feature I am working on next, I'm not going to bother with a more stringent check. * change version for dsp tools * Removed extra temporary file * Fixed merge bug * Fixed another merge bug * Removed commented out/unrelated files * Removed snake case
2016-10-11Scala style cleanup take 5 (#324)Chick Markley
* working through variable shrouding * working through variable shrouding * working through variable shadowing * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * Fixes suggested by Adam
2016-10-07Add test for Firrtl mems with no ports (#327)Jack Koenig
2016-10-07change default info mode to append (#328)Colin Schmidt
this makes it much easier to see where something went wrong during compilation if the lines have no info initially or its on internal nodes
2016-09-29Merge branch 'master' into fix_infer_mdirJim Lawson
2016-09-27eliminate postfix operator problematic statementschick
2016-09-27remove unnecessary parentheseschick
2016-09-27enclosing block redundantchick
2016-09-27No return type for implicit functionchick
2016-09-27Anonymous function convertible to a method valuechick
2016-09-26add CInferMDirSpecDonggyu Kim
2016-09-26fix CInferMDir on SubAccessDonggyu Kim
indices should be read ports
2016-09-26Added max width check to dshl shift amount (#318)Adam Izraelevitz
Address #297
2016-09-25Spec features added: AnalogType and Attach (#295)Adam Izraelevitz
* Spec features added: AnalogType and Attach AnalogType(width: Width): - Concrete syntax: wire x: AnalogType<10> - New groundtype, very restricted in use cases. - Can only declare ports and wires with Analog type - Analog types are never equivalent, thus if x and y have Analog types: x <= y is never legal. Attach(info: Info, source: Expression, exprs: Seq[Expression]): - Concrete syntax: attach x to (y, z) - New statement - Source can be any groundtyped expression (UInt, SInt, Analog, Clock) - Exprs must have an Analog type reference an instance port - Source and exprs must have identical widths Included WDefInstanceConnector to enable emission of Verilog inout Should be mostly feature complete. Need to update spec if PR gets accepted. * Fixed bug where invalidated ports aren't handled * Bugfix for VerilogPrep Intermediate wires for invalidated instance ports were not invalidated * Bugfix: calling create_exp with name/tpe Returns unknown gender, which was passing through Caused temporary wire to not be declared Because Verilog is dumb, undeclared wires are assumed to be 1bit signals * Addressed donggyukim's style comments * Reworked pass to only allow analog types in attach Restrict source to be only wire or port kind Much simpler implementation, almost identical functionality Clearer semantics (i think?) * Fixup bugs from pulling in new changes from master * comments for type eqs and small style fixes
2016-09-25offload latency pipe generation for memories from VerilogEmitterDonggyu Kim
discussed with @azidar
2016-09-25more readable verilog generation for register updatesDonggyu Kim
2016-09-25Syntactic sugar says use (A, B) instead of Tuple2[A, B]chick
2016-09-25use sys.error instead of deprecated errorchick
2016-09-25stuff like this mutable.LinkedHashMap needs the mutable prefixchick
2016-09-25remove unnecessary blockschick
example 1 s"${x}" example 2 case blah => { ??? }
2016-09-25implicit functions should specify return typechick
2016-09-25 use name parameter when calling a function with boolean constantchick
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