diff options
| author | chick | 2016-09-23 16:43:22 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-09-25 14:39:44 -0700 |
| commit | 93b5002cc18315b1872253926c3b383962bbb2d2 (patch) | |
| tree | 32db7158b180e188e19f36ee91dc55975f98fc28 /src | |
| parent | 1f168585c80d5c96e41353d6275d99b34b967b23 (diff) | |
stuff like this mutable.LinkedHashMap needs the mutable prefix
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 5 | ||||
| -rw-r--r-- | src/main/scala/firrtl/Namespace.scala | 3 | ||||
| -rw-r--r-- | src/main/scala/firrtl/Utils.scala | 6 |
3 files changed, 9 insertions, 5 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 2eaf5f36..1e7c3103 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -31,6 +31,7 @@ import com.typesafe.scalalogging.LazyLogging import java.nio.file.{Paths, Files} import java.io.{Reader, Writer} +import scala.collection.mutable import scala.sys.process._ import scala.io.Source @@ -245,7 +246,7 @@ class VerilogEmitter extends Emitter { } def emit_verilog(m: Module)(implicit w: Writer): DefModule = { - val netlist = LinkedHashMap[WrappedExpression, Expression]() + val netlist = mutable.LinkedHashMap[WrappedExpression, Expression]() val simlist = ArrayBuffer[Statement]() val namespace = Namespace(m) def build_netlist(s: Statement): Statement = s map build_netlist match { @@ -269,7 +270,7 @@ class VerilogEmitter extends Emitter { val declares = ArrayBuffer[Seq[Any]]() val instdeclares = ArrayBuffer[Seq[Any]]() val assigns = ArrayBuffer[Seq[Any]]() - val at_clock = LinkedHashMap[Expression,ArrayBuffer[Seq[Any]]]() + val at_clock = mutable.LinkedHashMap[Expression,ArrayBuffer[Seq[Any]]]() val initials = ArrayBuffer[Seq[Any]]() val simulates = ArrayBuffer[Seq[Any]]() def declare (b: String, n: String, t: Type) = t match { diff --git a/src/main/scala/firrtl/Namespace.scala b/src/main/scala/firrtl/Namespace.scala index 1e922673..4fbab779 100644 --- a/src/main/scala/firrtl/Namespace.scala +++ b/src/main/scala/firrtl/Namespace.scala @@ -27,6 +27,7 @@ MODIFICATIONS. package firrtl +import scala.collection.mutable import scala.collection.mutable.HashSet import firrtl.ir._ import Mappers._ @@ -34,7 +35,7 @@ import Mappers._ class Namespace private { private val tempNamePrefix: String = "GEN" // Begin with a tempNamePrefix in namespace so we always have a number suffix - private val namespace = HashSet[String](tempNamePrefix) + private val namespace = mutable.HashSet[String](tempNamePrefix) private var n = 0L def tryName(value: String): Boolean = { diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala index 685e0a9e..453e9a0c 100644 --- a/src/main/scala/firrtl/Utils.scala +++ b/src/main/scala/firrtl/Utils.scala @@ -41,6 +41,7 @@ import firrtl.PrimOps._ import firrtl.Mappers._ import firrtl.WrappedExpression._ import firrtl.WrappedType._ +import scala.collection.mutable import scala.collection.mutable.{StringBuilder, ArrayBuffer, LinkedHashMap, HashMap, HashSet} import java.io.PrintWriter import com.typesafe.scalalogging.LazyLogging @@ -144,6 +145,7 @@ object Utils extends LazyLogging { } /** Returns true if t, or any subtype, contains a flipped field + * * @param t type [[firrtl.ir.Type]] to be checked * @return if t contains [[firrtl.ir.Flip]] */ @@ -523,7 +525,7 @@ class MemoizedHash[T](val t: T) { * The graph is a map between the name of a node to set of names of that nodes children */ class ModuleGraph { - val nodes = HashMap[String, HashSet[String]]() + val nodes = mutable.HashMap[String, mutable.HashSet[String]]() /** * Add a child to a parent node @@ -534,7 +536,7 @@ class ModuleGraph { * @return a list indicating a path from child to parent, empty if no such path */ def add(parent: String, child: String): List[String] = { - val childSet = nodes.getOrElseUpdate(parent, new HashSet[String]) + val childSet = nodes.getOrElseUpdate(parent, new mutable.HashSet[String]) childSet += child pathExists(child, parent, List(child, parent)) } |
