Added max width check to dshl shift amount (#318)

Address #297

2 files changed, 24 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index e3c85edb..75b9a01d 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -565,6 +565,8 @@ object CheckWidths extends Pass {
     s"$info : [module $mname]  Uninferred width.")
   class WidthTooSmall(info: Info, mname: String, b: BigInt) extends PassException(
     s"$info : [module $mname]  Width too small for constant ${serialize(b)}.")
+  class WidthTooBig(info: Info, mname: String) extends PassException(
+    s"$info : [module $mname]  Width of dshl shift amount cannot be larger than 31 bits.")
   class NegWidthException(info:Info, mname: String) extends PassException(
     s"$info: [module $mname] Width cannot be negative or zero.")
   class BitsWidthException(info: Info, mname: String, hi: BigInt, width: BigInt) extends PassException(
@@ -608,6 +610,8 @@ object CheckWidths extends Pass {
           errors append new HeadWidthException(info, mname, n, bitWidth(a.tpe))
         case DoPrim(Tail, Seq(a), Seq(n), _) if bitWidth(a.tpe) <= n =>
           errors append new TailWidthException(info, mname, n, bitWidth(a.tpe))
+        case DoPrim(Dshl, Seq(a, b), _, _) if bitWidth(b.tpe) >= BigInt(32) =>
+          errors append new WidthTooBig(info, mname)
         case _ =>
       }
       e map check_width_w(info, mname) map check_width_e(info, mname)
diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala
index 4c9ad687..d1b16bb9 100644
--- a/src/test/scala/firrtlTests/WidthSpec.scala
+++ b/src/test/scala/firrtlTests/WidthSpec.scala
@@ -84,4 +84,24 @@ class WidthSpec extends FirrtlFlatSpec {
     val check = Seq( "output z : SInt<5>")
     executeTest(input, check, passes)
   }
+  "Dshl by 32 bits" should "result in an error" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes,
+      InferWidths,
+      CheckWidths)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    input x: UInt<3>
+        |    input y: UInt<32>
+        |    output z: UInt
+        |    z <= dshl(x, y)""".stripMargin
+    intercept[CheckWidths.WidthTooBig] {
+      executeTest(input, Nil, passes)
+    }
+  }
 }