| Age | Commit message (Collapse) | Author |
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Fixes #113 and Fixes #150
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Make EmptyExpression part of WIR
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Change Field from IsDeclaration to HasName
Make WDefInstance an IsDeclaration
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time uses LazyLogging, also delete import PrimOps._ (cyclic reference)
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the leaf directions are the same
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easier testing, because we don't the source locator information to say a test fails
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Also add pass to Verilog Compiler list of passes
This pass appends '_' to the names of aggregate types that would cause a name collision during LowerTypes.
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Make loweredName a public utility function of the Pass
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Almost all of the code was already there. This is cleaner (and faster)
than calling tpe(Expression).
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Legalize wasn't always doing its thing because of this.
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Fixes #134
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This allows the Print and Stop resulting from Chisel assertions to be guarded
by the same expression.
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This gives more expressions to eliminate
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Including using different clocks and ports defined in when scope.
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Invalidate clock at mem definition. Fixes #131
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This matches the unstated assumption in InferWidths.
Closes #135
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Change default print level to info.
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Replace use of gensym with local namespaces
Delete gensym
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Need many more, but this at least checks some DefMemory, DefRegister,
and keyword cases.
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