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authorAndrew Waterman2016-04-21 13:08:52 -0700
committerjackkoenig2016-04-21 15:54:02 -0700
commit811de1e3e4db77aa55c3b5a24dc78b13afb19a90 (patch)
tree7a1e67fccbfd8cc56bef6e1f73efb181eeffe8c7 /src
parent819285d3cf4a4a0a475819fff00fd8ccee51dac7 (diff)
Emit correct width for ConstProp'd bit extract
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/passes/ConstProp.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/ConstProp.scala b/src/main/scala/firrtl/passes/ConstProp.scala
index f891b58a..2a06c186 100644
--- a/src/main/scala/firrtl/passes/ConstProp.scala
+++ b/src/main/scala/firrtl/passes/ConstProp.scala
@@ -139,11 +139,11 @@ object ConstProp extends Pass {
case _ => e
}
case BITS_SELECT_OP => e.args(0) match {
- case UIntValue(v, w) => {
+ case UIntValue(v, _) => {
val hi = e.consts(0).toInt
val lo = e.consts(1).toInt
require(hi >= lo)
- UIntValue((v >> lo) & ((BigInt(1) << (hi - lo + 1)) - 1), w)
+ UIntValue((v >> lo) & ((BigInt(1) << (hi - lo + 1)) - 1), widthBANG(tpe(e)))
}
case x if long_BANG(tpe(e)) == long_BANG(tpe(x)) => tpe(x) match {
case t: UIntType => x