Fixed the check for bundle equality to allow relative flips to be wrong, but the leaf directions are the same

2 files changed, 53 insertions, 23 deletions

diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 76392982..f717b6ba 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -453,34 +453,35 @@ object CheckTypes extends Pass with LazyLogging {
          e
       }
    
-      def bulk_equals (t1:Type,t2:Type) : Boolean = {
-         (t1,t2) match { 
+      def bulk_equals (t1: Type, t2: Type, flip1: Flip, flip2: Flip): Boolean = {
+         //;println_all(["Inside with t1:" t1 ",t2:" t2 ",f1:" flip1 ",f2:" flip2])
+         (t1,t2) match {
+            case (t1:ClockType,t2:ClockType) => flip1 == flip2
+            case (t1:UIntType,t2:UIntType) => flip1 == flip2
+            case (t1:SIntType,t2:SIntType) => flip1 == flip2
             case (t1:BundleType,t2:BundleType) => {
-               var same = true
-               (t1.fields, t2.fields).zipped.map{ (f1,f2) => {
-                  if (f1.name == f2.name) {
-                     if (f1.flip != f2.flip) same = false
-                     if (!bulk_equals(f1.tpe,f2.tpe)) same = false
+               var isEqual = true
+               for (i <- 0 until t1.fields.size) {
+                  for (j <- 0 until t2.fields.size) {
+                     val f1 = t1.fields(i)
+                     val f2 = t2.fields(j)
+                     if (f1.name == f2.name) {
+                        val field_equal = bulk_equals(f1.tpe,f2.tpe,times(flip1, f1.flip),times(flip2, f2.flip))
+                        if (!field_equal) isEqual = false
+                     }
                   }
-               }}
-               same
-            }
-            case (t1:ClockType,t2:ClockType) => true
-            case (t1:UIntType,t2:UIntType) => true
-            case (t1:SIntType,t2:SIntType) => true
-            case (t1:VectorType,t2:VectorType) => {
-               if (bulk_equals(t1.tpe,t2.tpe)) true
-               else false
+               }
+               isEqual
             }
-            case (t1,t2) => false
+            case (t1:VectorType,t2:VectorType) => bulk_equals(t1.tpe,t2.tpe,flip1,flip2)
          }
       }
-           
+
       def check_types_s (s:Stmt) : Stmt = {
          s map (check_types_e(get_info(s))) match { 
             case (s:Connect) => if (wt(tpe(s.loc)) != wt(tpe(s.exp))) errors += new InvalidConnect(s.info)
             case (s:DefRegister) => if (wt(s.tpe) != wt(tpe(s.init))) errors += new InvalidRegInit(s.info)
-            case (s:BulkConnect) => if (!bulk_equals(tpe(s.loc),tpe(s.exp)) ) errors += new InvalidConnect(s.info)
+            case (s:BulkConnect) => if (!bulk_equals(tpe(s.loc),tpe(s.exp),DEFAULT,DEFAULT) ) errors += new InvalidConnect(s.info)
             case (s:Stop) => {
                if (wt(tpe(s.clk)) != wt(ClockType()) ) errors += new ReqClk(s.info)
                if (wt(tpe(s.en)) != wt(ut()) ) errors += new EnNotUInt(s.info)
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index 14e8562b..f8af4943 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -30,10 +30,11 @@ package firrtlTests
 import java.io._
 import org.scalatest._
 import org.scalatest.prop._
-import firrtl.{Parser,Circuit}
-import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassExceptions}
+import firrtl.{Parser,Circuit,FIRRTLEmitter}
+import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,ExpandConnects,PassExceptions}
 
 class UnitTests extends FlatSpec with Matchers {
+  def parse (input:String) = Parser.parse("",input.split("\n").toIterator,false)
   "Connecting bundles of different types" should "throw an exception" in {
     val passes = Seq(
       ToWorkingIR,
@@ -48,7 +49,7 @@ class UnitTests extends FlatSpec with Matchers {
         |    output x: {a : UInt<1>, b : UInt<1>}
         |    x <= y""".stripMargin
     intercept[PassExceptions] {
-      passes.foldLeft(Parser.parse("",input.split("\n").toIterator)) {
+      passes.foldLeft(parse(input)) {
         (c: Circuit, p: Pass) => p.run(c)
       }
     }
@@ -70,9 +71,37 @@ class UnitTests extends FlatSpec with Matchers {
        |    reg y : { valid : UInt<1>, bits : UInt<3> }, clk with :
        |      reset => (reset, x)""".stripMargin
     intercept[PassExceptions] {
-      passes.foldLeft(Parser.parse("",input.split("\n").toIterator)) {
+      passes.foldLeft(parse(input)) {
         (c: Circuit, p: Pass) => p.run(c)
       }
     }
   }
+
+  "Partial connection two bundle types whose relative flips don't match but leaf node directions do" should "connect correctly" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes,
+      ExpandConnects)
+    val input =
+     """circuit Unit :
+       |  module Unit :
+       |    wire x : { flip a: { b: UInt<32> } }
+       |    wire y : { a: { flip b: UInt<32> } }
+       |    x <- y""".stripMargin
+    val check =
+     """circuit Unit :
+       |  module Unit :
+       |    wire x : { flip a: { b: UInt<32> } }
+       |    wire y : { a: { flip b: UInt<32> } }
+       |    y.a.b <= x.a.b""".stripMargin
+    val c_result = passes.foldLeft(parse(input)) {
+      (c: Circuit, p: Pass) => p.run(c)
+    }
+    val writer = new StringWriter()
+    FIRRTLEmitter.run(c_result,writer)
+    (parse(writer.toString())) should be (parse(check))
+  }
 }