diff options
| author | Adam Izraelevitz | 2016-04-26 09:44:39 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-04-26 11:56:49 -0700 |
| commit | 7f81b4e89f15d8722e4907eb92c304c6ee438592 (patch) | |
| tree | c349fdcdd9e785c7aa250a67c5667d0ea69e677e /src | |
| parent | 770d781f0862a06b46267c7cdf7e99e406ef4423 (diff) | |
Add test for recursive check for whether BundleType contains flips
Diffstat (limited to 'src')
| -rw-r--r-- | src/test/scala/firrtlTests/CheckSpec.scala | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala new file mode 100644 index 00000000..4a646c38 --- /dev/null +++ b/src/test/scala/firrtlTests/CheckSpec.scala @@ -0,0 +1,28 @@ +package firrtlTests + +import java.io._ +import org.scalatest._ +import org.scalatest.prop._ +import firrtl.{Parser,Circuit} +import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassExceptions} + +class CheckSpec extends FlatSpec with Matchers { + "Connecting bundles of different types" should "throw an exception" in { + val passes = Seq( + ToWorkingIR, + CheckHighForm) + val input = + """circuit Unit : + | module Unit : + | mem m : + | data-type => {a : {b : {flip c : UInt<32>}}} + | depth => 32 + | read-latency => 0 + | write-latency => 1""".stripMargin + intercept[PassExceptions] { + passes.foldLeft(Parser.parse("",input.split("\n").toIterator)) { + (c: Circuit, p: Pass) => p.run(c) + } + } + } +} |
