diff options
| author | jackkoenig | 2016-04-21 12:40:05 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-04-21 12:40:05 -0700 |
| commit | 030145cec670feeffcb59c014637e38ca5067544 (patch) | |
| tree | 52695de6ea5b12e667041daa946d79aa2bb5f52c /src | |
| parent | d405203944b3a4c7b58a313c78268efc55899268 (diff) | |
Run Split Expressions before ConstProp, CSE, and DCE
This gives more expressions to eliminate
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Compiler.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala index 3b7b35fa..69450a67 100644 --- a/src/main/scala/firrtl/Compiler.scala +++ b/src/main/scala/firrtl/Compiler.scala @@ -83,11 +83,11 @@ object VerilogCompiler extends Compiler { InferTypes, ResolveGenders, InferWidths, + SplitExp, ConstProp, CommonSubexpressionElimination, DeadCodeElimination, VerilogWrap, - SplitExp, VerilogRename ) def run(c: Circuit, w: Writer) |