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Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Compiler.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala index 3b7b35fa..69450a67 100644 --- a/src/main/scala/firrtl/Compiler.scala +++ b/src/main/scala/firrtl/Compiler.scala @@ -83,11 +83,11 @@ object VerilogCompiler extends Compiler { InferTypes, ResolveGenders, InferWidths, + SplitExp, ConstProp, CommonSubexpressionElimination, DeadCodeElimination, VerilogWrap, - SplitExp, VerilogRename ) def run(c: Circuit, w: Writer) |