From 030145cec670feeffcb59c014637e38ca5067544 Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Thu, 21 Apr 2016 12:40:05 -0700
Subject: Run Split Expressions before ConstProp, CSE, and DCE

This gives more expressions to eliminate
---
 src/main/scala/firrtl/Compiler.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 3b7b35fa..69450a67 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -83,11 +83,11 @@ object VerilogCompiler extends Compiler {
     InferTypes,
     ResolveGenders,
     InferWidths,
+    SplitExp,
     ConstProp,
     CommonSubexpressionElimination,
     DeadCodeElimination,
     VerilogWrap,
-    SplitExp,
     VerilogRename
   )
   def run(c: Circuit, w: Writer)
-- 
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